kopia lustrzana https://github.com/espressif/esp-idf
467 wiersze
17 KiB
C
467 wiersze
17 KiB
C
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_ASSIST_DEBUG_STRUCT_H_
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#define _SOC_ASSIST_DEBUG_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct assist_debug_dev_s {
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union {
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struct {
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uint32_t core_0_area_dram0_0_rd : 1;
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uint32_t core_0_area_dram0_0_wr : 1;
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uint32_t core_0_area_dram0_1_rd : 1;
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uint32_t core_0_area_dram0_1_wr : 1;
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uint32_t core_0_area_pif_0_rd : 1;
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uint32_t core_0_area_pif_0_wr : 1;
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uint32_t core_0_area_pif_1_rd : 1;
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uint32_t core_0_area_pif_1_wr : 1;
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uint32_t core_0_sp_spill_min : 1;
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uint32_t core_0_sp_spill_max : 1;
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uint32_t core_0_iram0_exception_monitor: 1;
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uint32_t core_0_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_0_interrupt_ena;
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union {
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struct {
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uint32_t core_0_area_dram0_0_rd : 1;
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uint32_t core_0_area_dram0_0_wr : 1;
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uint32_t core_0_area_dram0_1_rd : 1;
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uint32_t core_0_area_dram0_1_wr : 1;
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uint32_t core_0_area_pif_0_rd : 1;
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uint32_t core_0_area_pif_0_wr : 1;
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uint32_t core_0_area_pif_1_rd : 1;
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uint32_t core_0_area_pif_1_wr : 1;
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uint32_t core_0_sp_spill_min : 1;
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uint32_t core_0_sp_spill_max : 1;
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uint32_t core_0_iram0_exception_monitor: 1;
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uint32_t core_0_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_0_interrupt_raw;
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union {
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struct {
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uint32_t core_0_area_dram0_0_rd : 1;
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uint32_t core_0_area_dram0_0_wr : 1;
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uint32_t core_0_area_dram0_1_rd : 1;
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uint32_t core_0_area_dram0_1_wr : 1;
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uint32_t core_0_area_pif_0_rd : 1;
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uint32_t core_0_area_pif_0_wr : 1;
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uint32_t core_0_area_pif_1_rd : 1;
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uint32_t core_0_area_pif_1_wr : 1;
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uint32_t core_0_sp_spill_min : 1;
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uint32_t core_0_sp_spill_max : 1;
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uint32_t core_0_iram0_exception_monitor: 1;
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uint32_t core_0_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_0_interrupt_rls;
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union {
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struct {
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uint32_t core_0_area_dram0_0_rd : 1;
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uint32_t core_0_area_dram0_0_wr : 1;
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uint32_t core_0_area_dram0_1_rd : 1;
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uint32_t core_0_area_dram0_1_wr : 1;
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uint32_t core_0_area_pif_0_rd : 1;
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uint32_t core_0_area_pif_0_wr : 1;
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uint32_t core_0_area_pif_1_rd : 1;
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uint32_t core_0_area_pif_1_wr : 1;
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uint32_t core_0_sp_spill_min : 1;
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uint32_t core_0_sp_spill_max : 1;
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uint32_t core_0_iram0_exception_monitor: 1;
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uint32_t core_0_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_0_interrupt_clr;
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uint32_t core_0_area_dram0_0_min;
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uint32_t core_0_area_dram0_0_max;
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uint32_t core_0_area_dram0_1_min;
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uint32_t core_0_area_dram0_1_max;
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uint32_t core_0_area_pif_0_min;
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uint32_t core_0_area_pif_0_max;
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uint32_t core_0_area_pif_1_min;
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uint32_t core_0_area_pif_1_max;
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uint32_t core_0_area_sp;
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uint32_t core_0_area_pc;
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union {
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struct {
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uint32_t core_0_sp_unstable : 8;
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uint32_t reserved8 : 24;
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};
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uint32_t val;
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} core_0_sp_unstable;
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uint32_t core_0_sp_min;
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uint32_t core_0_sp_max;
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uint32_t core_0_sp_pc;
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union {
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struct {
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uint32_t core_0_rcd_pdebugenable : 1;
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uint32_t reserved1 : 31;
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};
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uint32_t val;
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} core_0_rcd_pdebugenable;
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union {
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struct {
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uint32_t core_0_rcd_recording : 1;
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uint32_t reserved1 : 31;
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};
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uint32_t val;
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} core_0_rcd_recording;
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uint32_t core_0_rcd_pdebuginst;
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union {
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struct {
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uint32_t core_0_rcd_pdebugstatus : 8;
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uint32_t reserved8 : 24;
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};
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uint32_t val;
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} core_0_rcd_pdebugstatus;
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uint32_t core_0_rcd_pdebugdata;
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uint32_t core_0_rcd_pdebugpc;
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uint32_t core_0_rcd_pdebugls0stat;
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uint32_t core_0_rcd_pdebugls0addr;
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uint32_t core_0_rcd_pdebugls0data;
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uint32_t core_0_rcd_sp;
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union {
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struct {
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uint32_t core_0_iram0_recording_addr_0 : 24;
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uint32_t core_0_iram0_recording_wr_0 : 1;
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uint32_t core_0_iram0_recording_loadstore_0: 1;
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uint32_t reserved26 : 6;
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};
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uint32_t val;
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} core_0_iram0_exception_monitor_0;
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union {
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struct {
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uint32_t core_0_iram0_recording_addr_1 : 24;
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uint32_t core_0_iram0_recording_wr_1 : 1;
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uint32_t core_0_iram0_recording_loadstore_1: 1;
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uint32_t reserved26 : 6;
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};
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uint32_t val;
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} core_0_iram0_exception_monitor_1;
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union {
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struct {
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uint32_t core_0_dram0_recording_addr_0 : 22;
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uint32_t core_0_dram0_recording_wr_0 : 1;
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uint32_t reserved23 : 9;
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};
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uint32_t val;
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} core_0_dram0_exception_monitor_0;
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union {
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struct {
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uint32_t core_0_dram0_recording_byteen_0: 16;
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uint32_t reserved16 : 16;
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};
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uint32_t val;
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} core_0_dram0_exception_monitor_1;
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uint32_t core_0_dram0_exception_monitor_2;
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union {
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struct {
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uint32_t core_0_dram0_recording_addr_1 : 22;
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uint32_t core_0_dram0_recording_wr_1 : 1;
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uint32_t reserved23 : 9;
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};
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uint32_t val;
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} core_0_dram0_exception_monitor_3;
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union {
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struct {
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uint32_t core_0_dram0_recording_byteen_1: 16;
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uint32_t reserved16 : 16;
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};
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uint32_t val;
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} core_0_dram0_exception_monitor_4;
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uint32_t core_0_dram0_exception_monitor_5;
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union {
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struct {
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uint32_t core_1_area_dram0_0_rd : 1;
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uint32_t core_1_area_dram0_0_wr : 1;
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uint32_t core_1_area_dram0_1_rd : 1;
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uint32_t core_1_area_dram0_1_wr : 1;
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uint32_t core_1_area_pif_0_rd : 1;
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uint32_t core_1_area_pif_0_wr : 1;
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uint32_t core_1_area_pif_1_rd : 1;
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uint32_t core_1_area_pif_1_wr : 1;
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uint32_t core_1_sp_spill_min : 1;
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uint32_t core_1_sp_spill_max : 1;
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uint32_t core_1_iram0_exception_monitor: 1;
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uint32_t core_1_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_1_interrupt_ena;
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union {
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struct {
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uint32_t core_1_area_dram0_0_rd : 1;
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uint32_t core_1_area_dram0_0_wr : 1;
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uint32_t core_1_area_dram0_1_rd : 1;
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uint32_t core_1_area_dram0_1_wr : 1;
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uint32_t core_1_area_pif_0_rd : 1;
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uint32_t core_1_area_pif_0_wr : 1;
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uint32_t core_1_area_pif_1_rd : 1;
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uint32_t core_1_area_pif_1_wr : 1;
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uint32_t core_1_sp_spill_min : 1;
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uint32_t core_1_sp_spill_max : 1;
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uint32_t core_1_iram0_exception_monitor: 1;
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uint32_t core_1_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_1_interrupt_raw;
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union {
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struct {
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uint32_t core_1_area_dram0_0_rd : 1;
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uint32_t core_1_area_dram0_0_wr : 1;
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uint32_t core_1_area_dram0_1_rd : 1;
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uint32_t core_1_area_dram0_1_wr : 1;
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uint32_t core_1_area_pif_0_rd : 1;
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uint32_t core_1_area_pif_0_wr : 1;
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uint32_t core_1_area_pif_1_rd : 1;
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uint32_t core_1_area_pif_1_wr : 1;
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uint32_t core_1_sp_spill_min : 1;
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uint32_t core_1_sp_spill_max : 1;
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uint32_t core_1_iram0_exception_monitor: 1;
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uint32_t core_1_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_1_interrupt_rls;
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union {
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struct {
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uint32_t core_1_area_dram0_0_rd : 1;
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uint32_t core_1_area_dram0_0_wr : 1;
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uint32_t core_1_area_dram0_1_rd : 1;
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uint32_t core_1_area_dram0_1_wr : 1;
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uint32_t core_1_area_pif_0_rd : 1;
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uint32_t core_1_area_pif_0_wr : 1;
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uint32_t core_1_area_pif_1_rd : 1;
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uint32_t core_1_area_pif_1_wr : 1;
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uint32_t core_1_sp_spill_min : 1;
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uint32_t core_1_sp_spill_max : 1;
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uint32_t core_1_iram0_exception_monitor: 1;
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uint32_t core_1_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_1_interrupt_clr;
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uint32_t core_1_area_dram0_0_min;
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uint32_t core_1_area_dram0_0_max;
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uint32_t core_1_area_dram0_1_min;
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uint32_t core_1_area_dram0_1_max;
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uint32_t core_1_area_pif_0_min;
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uint32_t core_1_area_pif_0_max;
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uint32_t core_1_area_pif_1_min;
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uint32_t core_1_area_pif_1_max;
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uint32_t core_1_area_pc;
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uint32_t core_1_area_sp;
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union {
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struct {
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uint32_t core_1_sp_unstable : 8;
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uint32_t reserved8 : 24;
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};
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uint32_t val;
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} core_1_sp_unstable;
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uint32_t core_1_sp_min;
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uint32_t core_1_sp_max;
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uint32_t core_1_sp_pc;
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union {
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struct {
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uint32_t core_1_rcd_pdebugenable : 1;
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uint32_t reserved1 : 31;
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};
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uint32_t val;
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} core_1_rcd_pdebugenable;
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union {
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struct {
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uint32_t core_1_rcd_recording : 1;
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uint32_t reserved1 : 31;
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};
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uint32_t val;
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} core_1_rcd_recording;
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uint32_t core_1_rcd_pdebuginst;
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union {
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struct {
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uint32_t core_1_rcd_pdebugstatus : 8;
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uint32_t reserved8 : 24;
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};
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uint32_t val;
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} core_1_rcd_pdebugstatus;
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uint32_t core_1_rcd_pdebugdata;
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uint32_t core_1_rcd_pdebugpc;
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uint32_t core_1_rcd_pdebugls0stat;
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uint32_t core_1_rcd_pdebugls0addr;
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uint32_t core_1_rcd_pdebugls0data;
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uint32_t core_1_rcd_sp;
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union {
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struct {
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uint32_t core_1_iram0_recording_addr_0 : 24;
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uint32_t core_1_iram0_recording_wr_0 : 1;
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uint32_t core_1_iram0_recording_loadstore_0: 1;
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uint32_t reserved26 : 6;
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};
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uint32_t val;
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} core_1_iram0_exception_monitor_0;
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union {
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struct {
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uint32_t core_1_iram0_recording_addr_1 : 24;
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uint32_t core_1_iram0_recording_wr_1 : 1;
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uint32_t core_1_iram0_recording_loadstore_1: 1;
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uint32_t reserved26 : 6;
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};
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uint32_t val;
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} core_1_iram0_exception_monitor_1;
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union {
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struct {
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uint32_t core_1_dram0_recording_addr_0 : 22;
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uint32_t core_1_dram0_recording_wr_0 : 1;
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uint32_t reserved23 : 9;
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};
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uint32_t val;
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} core_1_dram0_exception_monitor_0;
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union {
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struct {
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uint32_t core_1_dram0_recording_byteen_0: 16;
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uint32_t reserved16 : 16;
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};
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uint32_t val;
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} core_1_dram0_exception_monitor_1;
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uint32_t core_1_dram0_exception_monitor_2;
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union {
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struct {
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uint32_t core_1_dram0_recording_addr_1 : 22;
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uint32_t core_1_dram0_recording_wr_1 : 1;
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uint32_t reserved23 : 9;
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};
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uint32_t val;
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} core_1_dram0_exception_monitor_3;
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union {
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struct {
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uint32_t core_1_dram0_recording_byteen_1: 16;
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uint32_t reserved16 : 16;
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};
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uint32_t val;
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} core_1_dram0_exception_monitor_4;
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uint32_t core_1_dram0_exception_monitor_5;
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union {
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struct {
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uint32_t core_x_iram0_dram0_limit_cycle_0: 20;
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uint32_t reserved20 : 12;
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};
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uint32_t val;
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} core_x_iram0_dram0_exception_monitor_0;
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union {
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struct {
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uint32_t core_x_iram0_dram0_limit_cycle_1: 20;
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uint32_t reserved20 : 12;
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};
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uint32_t val;
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} core_x_iram0_dram0_exception_monitor_1;
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union {
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struct {
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uint32_t log : 3;
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uint32_t log_mode : 3;
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uint32_t log_mem_loopble : 1;
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uint32_t reserved7 : 25;
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};
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uint32_t val;
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} log_setting;
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uint32_t log_data_0;
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uint32_t log_data_1;
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uint32_t log_data_2;
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uint32_t log_data_3;
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union {
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struct {
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uint32_t log_data_size : 16;
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uint32_t reserved16 : 16;
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};
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uint32_t val;
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} log_data_mask;
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uint32_t log_min;
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uint32_t log_max;
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uint32_t log_mem_start;
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uint32_t log_mem_end;
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uint32_t log_mem_writing_addr;
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union {
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struct {
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uint32_t log_mem_full_flag : 1;
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uint32_t reserved1 : 31;
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};
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uint32_t val;
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} log_mem_full_flag;
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uint32_t reserved_158;
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uint32_t reserved_15c;
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uint32_t reserved_160;
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uint32_t reserved_164;
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uint32_t reserved_168;
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uint32_t reserved_16c;
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uint32_t reserved_170;
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uint32_t reserved_174;
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uint32_t reserved_178;
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uint32_t reserved_17c;
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uint32_t reserved_180;
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uint32_t reserved_184;
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uint32_t reserved_188;
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uint32_t reserved_18c;
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uint32_t reserved_190;
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uint32_t reserved_194;
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uint32_t reserved_198;
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uint32_t reserved_19c;
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uint32_t reserved_1a0;
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|
uint32_t reserved_1a4;
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|
uint32_t reserved_1a8;
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|
uint32_t reserved_1ac;
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|
uint32_t reserved_1b0;
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|
uint32_t reserved_1b4;
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|
uint32_t reserved_1b8;
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|
uint32_t reserved_1bc;
|
|
uint32_t reserved_1c0;
|
|
uint32_t reserved_1c4;
|
|
uint32_t reserved_1c8;
|
|
uint32_t reserved_1cc;
|
|
uint32_t reserved_1d0;
|
|
uint32_t reserved_1d4;
|
|
uint32_t reserved_1d8;
|
|
uint32_t reserved_1dc;
|
|
uint32_t reserved_1e0;
|
|
uint32_t reserved_1e4;
|
|
uint32_t reserved_1e8;
|
|
uint32_t reserved_1ec;
|
|
uint32_t reserved_1f0;
|
|
uint32_t reserved_1f4;
|
|
uint32_t reserved_1f8;
|
|
union {
|
|
struct {
|
|
uint32_t assist_debug_reg_date : 28;
|
|
uint32_t reserved28 : 4;
|
|
};
|
|
uint32_t val;
|
|
} reg_date;
|
|
} assist_debug_dev_t;
|
|
extern assist_debug_dev_t ASSIST_DEBUG;
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
|
|
|
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#endif /*_SOC_ASSIST_DEBUG_STRUCT_H_ */
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