kopia lustrzana https://github.com/espressif/esp-idf
148 wiersze
4.6 KiB
C
148 wiersze
4.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The HAL layer for RTC CNTL (common part)
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#include "hal/rtc_hal.h"
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#include "soc/soc_caps.h"
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#include "esp32s3/rom/lldesc.h"
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#include "esp32s3/rom/cache.h"
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#include "hal/dma_types.h"
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#include "hal/assert.h"
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#include "esp_attr.h"
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#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */
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typedef struct rtc_cntl_link_buf_conf {
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uint32_t cfg[4]; /* 4 word for dma link buffer configuration */
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} rtc_cntl_link_buf_conf_t;
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void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
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{
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HAL_ASSERT(elem != NULL);
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HAL_ASSERT(buff != NULL);
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HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
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lldesc_t *plink = (lldesc_t *)elem;
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plink->eof = next ? 0 : 1;
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plink->owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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plink->size = size >> 4; /* in unit of 16 bytes */
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plink->length = size >> 4;
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plink->buf = buff;
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plink->offset = 0;
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plink->sosf = 0;
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STAILQ_NEXT(plink, qe) = next;
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return (void *)plink;
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}
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#if SOC_PM_SUPPORT_CPU_PD
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#define DEFAULT_RETENTION_WAIT_CYCLES (0x7f)
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#define DEFAULT_RETENTION_CLKOFF_WAIT_CYCLES (0xf)
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#define DEFAULT_RETENTION_DONE_WAIT_CYCLES (0x7)
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void rtc_cntl_hal_enable_cpu_retention(void *addr)
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{
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rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
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if (addr) {
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if (retent->cpu_pd_mem) {
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lldesc_t *plink = (lldesc_t *)retent->cpu_pd_mem;
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/* dma link buffer configure */
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rtc_cntl_link_buf_conf_t *pbuf = (rtc_cntl_link_buf_conf_t *)plink->buf;
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pbuf->cfg[0] = 0;
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pbuf->cfg[1] = 0;
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pbuf->cfg[2] = 0;
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pbuf->cfg[3] = 0xfffe0000;
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rtc_cntl_ll_set_cpu_retention_link_addr((uint32_t)plink);
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rtc_cntl_ll_config_cpu_retention_timing(
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DEFAULT_RETENTION_WAIT_CYCLES,
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DEFAULT_RETENTION_CLKOFF_WAIT_CYCLES,
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DEFAULT_RETENTION_DONE_WAIT_CYCLES
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);
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rtc_cntl_ll_enable_cpu_retention_clock();
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rtc_cntl_ll_enable_cpu_retention();
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}
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}
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}
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void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr)
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{
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rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
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if (addr) {
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if (retent->cpu_pd_mem) {
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/* I/d-cache tagmem retention has not been included or not
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* been enabled, after the system wakes up, all the contents
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* of i/d-cache need to be invalidated. */
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#if SOC_PM_SUPPORT_TAGMEM_PD
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if (!retent->tagmem.icache.enable) {
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Cache_Invalidate_ICache_All();
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}
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if (!retent->tagmem.dcache.enable) {
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Cache_Invalidate_DCache_All();
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}
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#else
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Cache_Invalidate_ICache_All();
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Cache_Invalidate_DCache_All();
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#endif // SOC_PM_SUPPORT_TAGMEM_PD
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rtc_cntl_ll_disable_cpu_retention();
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}
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}
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}
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#endif // SOC_PM_SUPPORT_CPU_PD
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#if SOC_PM_SUPPORT_TAGMEM_PD
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void rtc_cntl_hal_enable_tagmem_retention(void *addr)
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{
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rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
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if (addr) {
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if (retent->tagmem.link_addr) {
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rtc_cntl_ll_set_tagmem_retention_link_addr((uint32_t)(retent->tagmem.link_addr));
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rtc_cntl_ll_enable_tagmem_retention();
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if (retent->tagmem.icache.enable) {
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rtc_cntl_ll_enable_icache_tagmem_retention(
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retent->tagmem.icache.start_point,
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retent->tagmem.icache.vld_size,
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retent->tagmem.icache.size
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);
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}
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if (retent->tagmem.dcache.enable) {
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rtc_cntl_ll_enable_dcache_tagmem_retention(
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retent->tagmem.dcache.start_point,
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retent->tagmem.dcache.vld_size,
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retent->tagmem.dcache.size
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);
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}
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}
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}
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}
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void IRAM_ATTR rtc_cntl_hal_disable_tagmem_retention(void *addr)
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{
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rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
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if (addr) {
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if (retent->tagmem.link_addr) {
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rtc_cntl_ll_disable_tagmem_retention();
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if (retent->tagmem.icache.enable) {
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rtc_cntl_ll_disable_icache_tagmem_retention();
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}
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if (retent->tagmem.dcache.enable) {
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rtc_cntl_ll_disable_dcache_tagmem_retention();
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}
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}
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}
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}
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#endif // SOC_PM_SUPPORT_TAGMEM_PD
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