kopia lustrzana https://github.com/espressif/esp-idf
1045 wiersze
50 KiB
C
1045 wiersze
50 KiB
C
/**
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register
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* WIFI_MAC_INTR mapping register
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*/
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#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
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/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S)
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#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S 0
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/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register
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* WIFI_MAC_NMI mapping register
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*/
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#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
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/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP 0x0000003FU
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#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S)
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#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0
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/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register
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* WIFI_PWR_INTR mapping register
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*/
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#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
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/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S)
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#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S 0
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/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register
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* WIFI_BB_INTR mapping register
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*/
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#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc)
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/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S)
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#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S 0
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/** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register
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* BT_MAC_INTR mapping register
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*/
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#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
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/** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_BT_MAC_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S)
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#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S 0
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/** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register
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* BT_BB_INTR mapping register
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*/
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#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
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/** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_BT_BB_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_BT_BB_INTR_MAP_M (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S)
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#define INTERRUPT_CORE0_BT_BB_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_BT_BB_INTR_MAP_S 0
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/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register
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* BT_BB_NMI mapping register
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*/
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#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
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/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000003FU
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#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S)
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#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0
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/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register
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* LP_TIMER_INTR mapping register
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*/
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#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c)
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/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S)
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#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S 0
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/** INTERRUPT_CORE0_COEX_INTR_MAP_REG register
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* COEX_INTR mapping register
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*/
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#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
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/** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_COEX_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_COEX_INTR_MAP_M (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S)
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#define INTERRUPT_CORE0_COEX_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_COEX_INTR_MAP_S 0
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/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register
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* BLE_TIMER_INTR mapping register
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*/
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#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
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/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S)
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#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S 0
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/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register
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* BLE_SEC_INTR mapping register
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*/
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#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
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/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S)
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#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S 0
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/** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register
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* I2C_MST_INTR mapping register
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*/
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#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c)
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/** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_I2C_MST_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S)
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#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S 0
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/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register
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* ZB_MAC_INTR mapping register
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*/
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#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
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/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S)
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#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S 0
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/** INTERRUPT_CORE0_PMU_INTR_MAP_REG register
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* PMU_INTR mapping register
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*/
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#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
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/** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_PMU_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_PMU_INTR_MAP_M (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S)
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#define INTERRUPT_CORE0_PMU_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_PMU_INTR_MAP_S 0
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/** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register
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* EFUSE_INTR mapping register
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*/
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#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
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/** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_EFUSE_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_EFUSE_INTR_MAP_M (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S)
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#define INTERRUPT_CORE0_EFUSE_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_EFUSE_INTR_MAP_S 0
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/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
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* LP_RTC_TIMER_INTR mapping register
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*/
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#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c)
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/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S)
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#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S 0
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/** INTERRUPT_CORE0_LP_UART_INTR_MAP_REG register
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* LP_UART_INTR mapping register
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*/
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#define INTERRUPT_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
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/** INTERRUPT_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_LP_UART_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_LP_UART_INTR_MAP_M (INTERRUPT_CORE0_LP_UART_INTR_MAP_V << INTERRUPT_CORE0_LP_UART_INTR_MAP_S)
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#define INTERRUPT_CORE0_LP_UART_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_LP_UART_INTR_MAP_S 0
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/** INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG register
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* LP_I2C_INTR mapping register
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*/
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#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
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/** INTERRUPT_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_LP_I2C_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_M (INTERRUPT_CORE0_LP_I2C_INTR_MAP_V << INTERRUPT_CORE0_LP_I2C_INTR_MAP_S)
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#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_S 0
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/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register
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* LP_WDT_INTR mapping register
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*/
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#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
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/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_LP_WDT_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S)
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#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S 0
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/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
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* LP_PERI_TIMEOUT_INTR mapping register
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*/
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#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c)
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/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
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#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0
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/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register
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* LP_APM_M0_INTR mapping register
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*/
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#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
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/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S)
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#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S 0
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/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG register
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* LP_APM_M1_INTR mapping register
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*/
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#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
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/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S)
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#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S 0
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/** INTERRUPT_CORE0_HUK_INTR_MAP_REG register
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* HUK_INTR mapping register
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*/
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#define INTERRUPT_CORE0_HUK_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
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/** INTERRUPT_CORE0_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_HUK_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_HUK_INTR_MAP_M (INTERRUPT_CORE0_HUK_INTR_MAP_V << INTERRUPT_CORE0_HUK_INTR_MAP_S)
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#define INTERRUPT_CORE0_HUK_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_HUK_INTR_MAP_S 0
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/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
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* CPU_INTR_FROM_CPU_0 mapping register
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*/
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c)
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/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000003FU
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
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/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
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* CPU_INTR_FROM_CPU_1 mapping register
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*/
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
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/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000003FU
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000003FU
|
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
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|
|
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/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
|
|
* CPU_INTR_FROM_CPU_2 mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
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/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000003FU
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
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|
|
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/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
|
|
* CPU_INTR_FROM_CPU_3 mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
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/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000003FU
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
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|
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/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
|
|
* ASSIST_DEBUG_INTR mapping register
|
|
*/
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#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c)
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/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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|
*/
|
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#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)
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#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
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|
|
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/** INTERRUPT_CORE0_TRACE_INTR_MAP_REG register
|
|
* TRACE_INTR mapping register
|
|
*/
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#define INTERRUPT_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
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/** INTERRUPT_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_TRACE_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_TRACE_INTR_MAP_M (INTERRUPT_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_TRACE_INTR_MAP_S)
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#define INTERRUPT_CORE0_TRACE_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_TRACE_INTR_MAP_S 0
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|
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/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register
|
|
* CACHE_INTR mapping register
|
|
*/
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#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
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/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
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|
#define INTERRUPT_CORE0_CACHE_INTR_MAP 0x0000003FU
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|
#define INTERRUPT_CORE0_CACHE_INTR_MAP_M (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S)
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#define INTERRUPT_CORE0_CACHE_INTR_MAP_V 0x0000003FU
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|
#define INTERRUPT_CORE0_CACHE_INTR_MAP_S 0
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|
|
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/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
|
|
* CPU_PERI_TIMEOUT_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
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|
/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
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#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0
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|
|
|
/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
|
|
* GPIO_INTERRUPT_PRO mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c)
|
|
/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
|
|
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG register
|
|
* GPIO_INTERRUPT_EXT mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
|
|
/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S)
|
|
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register
|
|
* PAU_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
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|
/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_PAU_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_PAU_INTR_MAP_M (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_PAU_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_PAU_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
|
|
* HP_PERI_TIMEOUT_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
|
|
/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
|
|
* MODEM_PERI_TIMEOUT_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
|
|
/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register
|
|
* HP_APM_M0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
|
|
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register
|
|
* HP_APM_M1_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
|
|
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register
|
|
* HP_APM_M2_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
|
|
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register
|
|
* HP_APM_M3_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
|
|
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register
|
|
* HP_APM_M4_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
|
|
/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG register
|
|
* LP_APM0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4)
|
|
/** INTERRUPT_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_LP_APM0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register
|
|
* MSPI_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8)
|
|
/** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_MSPI_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_MSPI_INTR_MAP_M (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_I2S_INTR_MAP_REG register
|
|
* I2S_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
|
|
/** INTERRUPT_CORE0_I2S_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_I2S_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_I2S_INTR_MAP_M (INTERRUPT_CORE0_I2S_INTR_MAP_V << INTERRUPT_CORE0_I2S_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_I2S_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_I2S_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register
|
|
* UHCI0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0)
|
|
/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register
|
|
* UART0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4)
|
|
/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_UART0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_UART0_INTR_MAP_M (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_UART0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_UART0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register
|
|
* UART1_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8)
|
|
/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register
|
|
* LEDC_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc)
|
|
/** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_LEDC_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_LEDC_INTR_MAP_M (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_TWAI0_INTR_MAP_REG register
|
|
* TWAI0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
|
|
/** INTERRUPT_CORE0_TWAI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_TWAI0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_M (INTERRUPT_CORE0_TWAI0_INTR_MAP_V << INTERRUPT_CORE0_TWAI0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG register
|
|
* TWAI0_TIMER_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
|
|
/** INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_M (INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_V << INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_TWAI1_INTR_MAP_REG register
|
|
* TWAI1_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
|
|
/** INTERRUPT_CORE0_TWAI1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_TWAI1_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_M (INTERRUPT_CORE0_TWAI1_INTR_MAP_V << INTERRUPT_CORE0_TWAI1_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG register
|
|
* TWAI1_TIMER_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
|
|
/** INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_M (INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_V << INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG register
|
|
* USB_SERIAL_JTAG_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
|
|
/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_M (INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V << INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register
|
|
* RMT_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
|
|
/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_RMT_INTR_MAP_M (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register
|
|
* I2C_EXT0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
|
|
/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register
|
|
* TG0_T0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
|
|
/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register
|
|
* TG0_WDT_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
|
|
/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register
|
|
* TG1_T0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
|
|
/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register
|
|
* TG1_WDT_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8)
|
|
/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
|
|
* SYSTIMER_TARGET0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec)
|
|
/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
|
|
* SYSTIMER_TARGET1_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0)
|
|
/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
|
|
* SYSTIMER_TARGET2_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4)
|
|
/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register
|
|
* APB_ADC_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8)
|
|
/** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_PWM_INTR_MAP_REG register
|
|
* PWM_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc)
|
|
/** INTERRUPT_CORE0_PWM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_PWM_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_PWM_INTR_MAP_M (INTERRUPT_CORE0_PWM_INTR_MAP_V << INTERRUPT_CORE0_PWM_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_PWM_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_PWM_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_PCNT_INTR_MAP_REG register
|
|
* PCNT_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
|
|
/** INTERRUPT_CORE0_PCNT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_PCNT_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_PCNT_INTR_MAP_M (INTERRUPT_CORE0_PCNT_INTR_MAP_V << INTERRUPT_CORE0_PCNT_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_PCNT_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_PCNT_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG register
|
|
* PARL_IO_TX_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
|
|
/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_M (INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG register
|
|
* PARL_IO_RX_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
|
|
/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_M (INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register
|
|
* DMA_IN_CH0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
|
|
/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register
|
|
* DMA_IN_CH1_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
|
|
/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register
|
|
* DMA_IN_CH2_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
|
|
/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
|
|
* DMA_OUT_CH0_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
|
|
/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
|
|
* DMA_OUT_CH1_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
|
|
/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
|
|
* DMA_OUT_CH2_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
|
|
/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register
|
|
* GPSPI2_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
|
|
/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP 0x0000003FU
|
|
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S)
|
|
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V 0x0000003FU
|
|
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S 0
|
|
|
|
/** INTERRUPT_CORE0_AES_INTR_MAP_REG register
|
|
* AES_INTR mapping register
|
|
*/
|
|
#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
|
|
/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
|
* Configures the interrupt source into one CPU interrupt.
|
|
*/
|
|
#define INTERRUPT_CORE0_AES_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_AES_INTR_MAP_M (INTERRUPT_CORE0_AES_INTR_MAP_V << INTERRUPT_CORE0_AES_INTR_MAP_S)
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#define INTERRUPT_CORE0_AES_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_AES_INTR_MAP_S 0
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/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register
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* SHA_INTR mapping register
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*/
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#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
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/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_SHA_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_SHA_INTR_MAP_M (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S)
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#define INTERRUPT_CORE0_SHA_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_SHA_INTR_MAP_S 0
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/** INTERRUPT_CORE0_RSA_INTR_MAP_REG register
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* RSA_INTR mapping register
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*/
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#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
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/** INTERRUPT_CORE0_RSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_RSA_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_RSA_INTR_MAP_M (INTERRUPT_CORE0_RSA_INTR_MAP_V << INTERRUPT_CORE0_RSA_INTR_MAP_S)
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#define INTERRUPT_CORE0_RSA_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_RSA_INTR_MAP_S 0
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/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register
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* ECC_INTR mapping register
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*/
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#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
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/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_ECC_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_ECC_INTR_MAP_M (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S)
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#define INTERRUPT_CORE0_ECC_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_ECC_INTR_MAP_S 0
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/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register
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* ECDSA_INTR mapping register
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*/
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#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
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/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_ECDSA_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_ECDSA_INTR_MAP_M (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S)
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#define INTERRUPT_CORE0_ECDSA_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_ECDSA_INTR_MAP_S 0
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/** INTERRUPT_CORE0_KM_INTR_MAP_REG register
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* KM_INTR mapping register
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*/
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#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
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/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
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* Configures the interrupt source into one CPU interrupt.
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*/
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#define INTERRUPT_CORE0_KM_INTR_MAP 0x0000003FU
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#define INTERRUPT_CORE0_KM_INTR_MAP_M (INTERRUPT_CORE0_KM_INTR_MAP_V << INTERRUPT_CORE0_KM_INTR_MAP_S)
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#define INTERRUPT_CORE0_KM_INTR_MAP_V 0x0000003FU
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#define INTERRUPT_CORE0_KM_INTR_MAP_S 0
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/** INTERRUPT_CORE0_INT_STATUS_0_REG register
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* Status register for interrupt sources 0 ~ 31
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*/
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#define INTERRUPT_CORE0_INT_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
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/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
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* Represents the status of the interrupt sources numbered from .Each bit corresponds
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* to one interrupt source
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* 0:The corresponding interrupt source triggered an interrupt
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* 1:No interrupt triggered
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*/
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#define INTERRUPT_CORE0_INT_STATUS_0 0xFFFFFFFFU
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#define INTERRUPT_CORE0_INT_STATUS_0_M (INTERRUPT_CORE0_INT_STATUS_0_V << INTERRUPT_CORE0_INT_STATUS_0_S)
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#define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU
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#define INTERRUPT_CORE0_INT_STATUS_0_S 0
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/** INTERRUPT_CORE0_INT_STATUS_1_REG register
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* Status register for interrupt sources 32 ~ 63
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*/
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#define INTERRUPT_CORE0_INT_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
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/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
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* Represents the status of the interrupt sources numbered from .Each bit corresponds
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* to one interrupt source
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* 0:The corresponding interrupt source triggered an interrupt
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* 1:No interrupt triggered
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*/
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#define INTERRUPT_CORE0_INT_STATUS_1 0xFFFFFFFFU
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#define INTERRUPT_CORE0_INT_STATUS_1_M (INTERRUPT_CORE0_INT_STATUS_1_V << INTERRUPT_CORE0_INT_STATUS_1_S)
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#define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU
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#define INTERRUPT_CORE0_INT_STATUS_1_S 0
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/** INTERRUPT_CORE0_INT_STATUS_2_REG register
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* Status register for interrupt sources 64 ~ 95
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*/
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#define INTERRUPT_CORE0_INT_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
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/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
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* Represents the status of the interrupt sources numbered from .Each bit corresponds
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* to one interrupt source
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* 0:The corresponding interrupt source triggered an interrupt
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* 1:No interrupt triggered
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*/
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#define INTERRUPT_CORE0_INT_STATUS_2 0xFFFFFFFFU
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#define INTERRUPT_CORE0_INT_STATUS_2_M (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S)
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#define INTERRUPT_CORE0_INT_STATUS_2_V 0xFFFFFFFFU
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#define INTERRUPT_CORE0_INT_STATUS_2_S 0
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/** INTERRUPT_CORE0_CLOCK_GATE_REG register
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* Interrupt clock gating configure register
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*/
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#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
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/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
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* Interrupt clock gating configure register
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*/
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#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0))
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#define INTERRUPT_CORE0_REG_CLK_EN_M (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S)
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#define INTERRUPT_CORE0_REG_CLK_EN_V 0x00000001U
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#define INTERRUPT_CORE0_REG_CLK_EN_S 0
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/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register
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* Version control register
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*/
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#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc)
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/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36773985;
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* Version control register
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*/
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#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU
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#define INTERRUPT_CORE0_INTERRUPT_DATE_M (INTERRUPT_CORE0_INTERRUPT_DATE_V << INTERRUPT_CORE0_INTERRUPT_DATE_S)
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#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0x0FFFFFFFU
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#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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