kopia lustrzana https://github.com/espressif/esp-idf
417 wiersze
16 KiB
C
417 wiersze
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <inttypes.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "unity.h"
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#include "esp_heap_caps.h"
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#include "esp_private/gdma.h"
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#include "hal/dma_types.h"
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#include "soc/soc_caps.h"
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#include "hal/gdma_ll.h"
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#include "hal/cache_ll.h"
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#include "esp_cache.h"
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TEST_CASE("GDMA channel allocation", "[GDMA]")
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{
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gdma_channel_alloc_config_t channel_config = {};
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gdma_channel_handle_t tx_channels[SOC_GDMA_PAIRS_PER_GROUP_MAX] = {};
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gdma_channel_handle_t rx_channels[SOC_GDMA_PAIRS_PER_GROUP_MAX] = {};
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channel_config.direction = GDMA_CHANNEL_DIRECTION_TX;
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#if SOC_AHB_GDMA_SUPPORTED
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// install TX channels
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for (int i = 0; i < GDMA_LL_AHB_PAIRS_PER_GROUP; i++) {
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TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channels[i]));
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};
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TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_ahb_channel(&channel_config, &tx_channels[0]));
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// Free interrupts before installing RX interrupts to ensure enough free interrupts
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for (int i = 0; i < GDMA_LL_AHB_PAIRS_PER_GROUP; i++) {
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TEST_ESP_OK(gdma_del_channel(tx_channels[i]));
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}
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// install RX channels
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channel_config.direction = GDMA_CHANNEL_DIRECTION_RX;
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for (int i = 0; i < GDMA_LL_AHB_PAIRS_PER_GROUP; i++) {
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TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &rx_channels[i]));
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}
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TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_ahb_channel(&channel_config, &rx_channels[0]));
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for (int i = 0; i < GDMA_LL_AHB_PAIRS_PER_GROUP; i++) {
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TEST_ESP_OK(gdma_del_channel(rx_channels[i]));
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}
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#endif // SOC_AHB_GDMA_SUPPORTED
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// install single and paired TX/RX channels
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#if GDMA_LL_AHB_PAIRS_PER_GROUP >= 2
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// single tx channel
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channel_config.direction = GDMA_CHANNEL_DIRECTION_TX;
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TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channels[0]));
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// create tx channel and reserve sibling
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channel_config.direction = GDMA_CHANNEL_DIRECTION_TX;
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channel_config.flags.reserve_sibling = 1;
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TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channels[1]));
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// create rx channel and specify sibling channel
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channel_config.flags.reserve_sibling = 0;
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channel_config.sibling_chan = tx_channels[1]; // specify sibling channel
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channel_config.direction = GDMA_CHANNEL_DIRECTION_RX;
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TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &rx_channels[1]));
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channel_config.sibling_chan = NULL;
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TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &rx_channels[0]));
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TEST_ESP_OK(gdma_connect(tx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0)));
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// can't connect multiple channels to the same peripheral
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TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0)));
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TEST_ESP_OK(gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0)));
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TEST_ESP_OK(gdma_connect(rx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0)));
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// but rx and tx can connect to the same peripheral
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TEST_ESP_OK(gdma_connect(rx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0)));
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for (int i = 0; i < 2; i++) {
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TEST_ESP_OK(gdma_disconnect(tx_channels[i]));
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TEST_ESP_OK(gdma_disconnect(rx_channels[i]));
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TEST_ESP_OK(gdma_del_channel(tx_channels[i]));
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TEST_ESP_OK(gdma_del_channel(rx_channels[i]));
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}
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#endif // GDMA_LL_AHB_PAIRS_PER_GROUP >= 2
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#if SOC_AXI_GDMA_SUPPORTED
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// install TX channels
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channel_config.direction = GDMA_CHANNEL_DIRECTION_TX;
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for (int i = 0; i < GDMA_LL_AXI_PAIRS_PER_GROUP; i++) {
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TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &tx_channels[i]));
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};
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TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_axi_channel(&channel_config, &tx_channels[0]));
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// Free interrupts before installing RX interrupts to ensure enough free interrupts
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for (int i = 0; i < GDMA_LL_AXI_PAIRS_PER_GROUP; i++) {
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TEST_ESP_OK(gdma_del_channel(tx_channels[i]));
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}
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// install RX channels
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channel_config.direction = GDMA_CHANNEL_DIRECTION_RX;
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for (int i = 0; i < GDMA_LL_AXI_PAIRS_PER_GROUP; i++) {
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TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &rx_channels[i]));
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}
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TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, gdma_new_axi_channel(&channel_config, &rx_channels[0]));
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for (int i = 0; i < GDMA_LL_AXI_PAIRS_PER_GROUP; i++) {
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TEST_ESP_OK(gdma_del_channel(rx_channels[i]));
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}
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#endif // SOC_AXI_GDMA_SUPPORTED
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// install single and paired TX/RX channels
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#if GDMA_LL_AXI_PAIRS_PER_GROUP >= 2
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// single tx channel
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channel_config.direction = GDMA_CHANNEL_DIRECTION_TX;
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TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &tx_channels[0]));
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// create tx channel and reserve sibling
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channel_config.direction = GDMA_CHANNEL_DIRECTION_TX;
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channel_config.flags.reserve_sibling = 1;
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TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &tx_channels[1]));
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// create rx channel and specify sibling channel
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channel_config.flags.reserve_sibling = 0;
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channel_config.sibling_chan = tx_channels[1]; // specify sibling channel
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channel_config.direction = GDMA_CHANNEL_DIRECTION_RX;
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TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &rx_channels[1]));
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channel_config.sibling_chan = NULL;
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TEST_ESP_OK(gdma_new_axi_channel(&channel_config, &rx_channels[0]));
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TEST_ESP_OK(gdma_connect(tx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)));
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// can't connect multiple channels to the same peripheral
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TEST_ESP_ERR(ESP_ERR_INVALID_STATE, gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)));
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TEST_ESP_OK(gdma_connect(tx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0)));
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TEST_ESP_OK(gdma_connect(rx_channels[0], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)));
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// but rx and tx can connect to the same peripheral
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TEST_ESP_OK(gdma_connect(rx_channels[1], GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0)));
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for (int i = 0; i < 2; i++) {
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TEST_ESP_OK(gdma_disconnect(tx_channels[i]));
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TEST_ESP_OK(gdma_disconnect(rx_channels[i]));
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TEST_ESP_OK(gdma_del_channel(tx_channels[i]));
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TEST_ESP_OK(gdma_del_channel(rx_channels[i]));
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}
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#endif // GDMA_LL_AXI_PAIRS_PER_GROUP >= 2
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}
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static bool test_gdma_m2m_rx_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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{
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BaseType_t task_woken = pdFALSE;
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SemaphoreHandle_t done_sem = (SemaphoreHandle_t)user_data;
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xSemaphoreGiveFromISR(done_sem, &task_woken);
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return task_woken == pdTRUE;
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}
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static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan)
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{
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gdma_rx_event_callbacks_t rx_cbs = {
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.on_recv_eof = test_gdma_m2m_rx_eof_callback,
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};
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SemaphoreHandle_t done_sem = xSemaphoreCreateBinary();
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TEST_ESP_OK(gdma_register_rx_event_callbacks(rx_chan, &rx_cbs, done_sem));
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gdma_strategy_config_t strategy = {
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.auto_update_desc = true,
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.owner_check = true,
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};
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TEST_ESP_OK(gdma_apply_strategy(tx_chan, &strategy));
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TEST_ESP_OK(gdma_apply_strategy(rx_chan, &strategy));
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gdma_trigger_t m2m_trigger = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0);
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// get a free DMA trigger ID for memory copy
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uint32_t free_m2m_id_mask = 0;
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gdma_get_free_m2m_trig_id_mask(tx_chan, &free_m2m_id_mask);
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m2m_trigger.instance_id = __builtin_ctz(free_m2m_id_mask);
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TEST_ESP_OK(gdma_connect(tx_chan, m2m_trigger));
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TEST_ESP_OK(gdma_connect(rx_chan, m2m_trigger));
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uint8_t *src_buf = heap_caps_aligned_alloc(64, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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uint8_t *dst_buf = heap_caps_aligned_alloc(64, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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TEST_ASSERT_NOT_NULL(src_buf);
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TEST_ASSERT_NOT_NULL(dst_buf);
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memset(src_buf, 0, 256);
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memset(dst_buf, 0, 256);
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dma_descriptor_align8_t *tx_descs = (dma_descriptor_align8_t *) src_buf;
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dma_descriptor_align8_t *rx_descs = (dma_descriptor_align8_t *) dst_buf;
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uint8_t *src_data = src_buf + 64;
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uint8_t *dst_data = dst_buf + 64;
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// prepare the source data
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for (int i = 0; i < 128; i++) {
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src_data[i] = i;
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}
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#if CONFIG_IDF_TARGET_ESP32P4
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// CPU and DMA both can write to the DMA descriptor, so if there is a cache, multiple descriptors may reside in the same cache line
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// causing data inconsistency. To avoid this, we want to access the descriptor memory without the cache.
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dma_descriptor_align8_t *tx_descs_noncache = (dma_descriptor_align8_t *)(CACHE_LL_L2MEM_NON_CACHE_ADDR(tx_descs));
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dma_descriptor_align8_t *rx_descs_noncache = (dma_descriptor_align8_t *)(CACHE_LL_L2MEM_NON_CACHE_ADDR(rx_descs));
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tx_descs_noncache[0].buffer = src_data;
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tx_descs_noncache[0].dw0.size = 64;
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tx_descs_noncache[0].dw0.length = 64;
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tx_descs_noncache[0].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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tx_descs_noncache[0].dw0.suc_eof = 0;
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tx_descs_noncache[0].next = &tx_descs[1]; // Note, the DMA doesn't recognize a non-cacheable address, here must be the cached address
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tx_descs_noncache[1].buffer = src_data + 64;
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tx_descs_noncache[1].dw0.size = 64;
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tx_descs_noncache[1].dw0.length = 64;
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tx_descs_noncache[1].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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tx_descs_noncache[1].dw0.suc_eof = 1;
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tx_descs_noncache[1].next = NULL;
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rx_descs_noncache->buffer = dst_data;
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rx_descs_noncache->dw0.size = 128;
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rx_descs_noncache->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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rx_descs_noncache->dw0.suc_eof = 1;
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rx_descs_noncache->next = NULL;
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#else
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tx_descs->buffer = src_data;
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tx_descs->dw0.size = 128;
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tx_descs->dw0.length = 128;
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tx_descs->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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tx_descs->dw0.suc_eof = 1;
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tx_descs->next = NULL;
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rx_descs->buffer = dst_data;
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rx_descs->dw0.size = 128;
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rx_descs->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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rx_descs->next = NULL;
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#endif
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#if CONFIG_IDF_TARGET_ESP32P4
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// do write-back for the source data because it's in the cache
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TEST_ESP_OK(esp_cache_msync((void *)src_data, 128, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
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#endif
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TEST_ESP_OK(gdma_start(rx_chan, (intptr_t)rx_descs));
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TEST_ESP_OK(gdma_start(tx_chan, (intptr_t)tx_descs));
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xSemaphoreTake(done_sem, portMAX_DELAY);
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#if CONFIG_IDF_TARGET_ESP32P4
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// the destination data are not reflected to the cache, so do an invalidate to ask the cache load new data
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TEST_ESP_OK(esp_cache_msync((void *)dst_data, 128, ESP_CACHE_MSYNC_FLAG_DIR_M2C));
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#endif
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// check the DMA descriptor write-back feature
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TEST_ASSERT_EQUAL(DMA_DESCRIPTOR_BUFFER_OWNER_CPU, tx_descs[0].dw0.owner);
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TEST_ASSERT_EQUAL(DMA_DESCRIPTOR_BUFFER_OWNER_CPU, rx_descs[0].dw0.owner);
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for (int i = 0; i < 128; i++) {
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TEST_ASSERT_EQUAL(i, dst_data[i]);
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}
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free((void *)src_buf);
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free((void *)dst_buf);
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vSemaphoreDelete(done_sem);
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}
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TEST_CASE("GDMA M2M Mode", "[GDMA]")
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{
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gdma_channel_handle_t tx_chan = NULL;
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gdma_channel_handle_t rx_chan = NULL;
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gdma_channel_alloc_config_t tx_chan_alloc_config = {};
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gdma_channel_alloc_config_t rx_chan_alloc_config = {};
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#if SOC_AHB_GDMA_SUPPORTED
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tx_chan_alloc_config = (gdma_channel_alloc_config_t) {
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.direction = GDMA_CHANNEL_DIRECTION_TX,
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.flags.reserve_sibling = true,
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};
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TEST_ESP_OK(gdma_new_ahb_channel(&tx_chan_alloc_config, &tx_chan));
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rx_chan_alloc_config = (gdma_channel_alloc_config_t) {
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.direction = GDMA_CHANNEL_DIRECTION_RX,
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.sibling_chan = tx_chan,
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};
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TEST_ESP_OK(gdma_new_ahb_channel(&rx_chan_alloc_config, &rx_chan));
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test_gdma_m2m_mode(tx_chan, rx_chan);
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TEST_ESP_OK(gdma_del_channel(tx_chan));
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TEST_ESP_OK(gdma_del_channel(rx_chan));
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#endif // SOC_AHB_GDMA_SUPPORTED
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#if SOC_AXI_GDMA_SUPPORTED
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tx_chan_alloc_config = (gdma_channel_alloc_config_t) {
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.direction = GDMA_CHANNEL_DIRECTION_TX,
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.flags.reserve_sibling = true,
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};
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TEST_ESP_OK(gdma_new_axi_channel(&tx_chan_alloc_config, &tx_chan));
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rx_chan_alloc_config = (gdma_channel_alloc_config_t) {
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.direction = GDMA_CHANNEL_DIRECTION_RX,
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.sibling_chan = tx_chan,
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};
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TEST_ESP_OK(gdma_new_axi_channel(&rx_chan_alloc_config, &rx_chan));
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test_gdma_m2m_mode(tx_chan, rx_chan);
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TEST_ESP_OK(gdma_del_channel(tx_chan));
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TEST_ESP_OK(gdma_del_channel(rx_chan));
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#endif // SOC_AXI_GDMA_SUPPORTED
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}
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#if SOC_GDMA_SUPPORT_CRC
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typedef struct {
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uint32_t init_value;
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uint32_t crc_bit_width;
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uint32_t poly_hex;
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bool reverse_data_mask;
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uint32_t expected_result;
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} test_crc_case_t;
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static test_crc_case_t crc_test_cases[] = {
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// CRC8, x^8+x^2+x+1
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[0] = {
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.crc_bit_width = 8,
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.init_value = 0x00,
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.poly_hex = 0x07,
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.expected_result = 0xC6,
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},
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[1] = {
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.crc_bit_width = 8,
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.init_value = 0x00,
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.poly_hex = 0x07,
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.reverse_data_mask = true, // refin = true
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.expected_result = 0xDE,
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},
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// CRC16, x^16+x^12+x^5+1
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[2] = {
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.crc_bit_width = 16,
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.init_value = 0xFFFF,
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.poly_hex = 0x1021,
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.expected_result = 0x5289,
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},
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// CRC32, x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
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[3] = {
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.crc_bit_width = 32,
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.init_value = 0xFFFFFFFF,
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.poly_hex = 0x04C11DB7,
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.expected_result = 0x63B3E283,
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}
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};
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// CRC online: https://www.lddgo.net/en/encrypt/crc
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static void test_gdma_crc_calculation(gdma_channel_handle_t tx_chan, int test_num_crc_algorithm)
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{
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uint32_t crc_result = 0;
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const char *test_input_string = "Share::Connect::Innovate";
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size_t input_data_size = strlen(test_input_string);
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printf("Calculate CRC value for string: \"%s\"\r\n", test_input_string);
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gdma_trigger_t m2m_trigger = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0);
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// get a free DMA trigger ID
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uint32_t free_m2m_id_mask = 0;
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gdma_get_free_m2m_trig_id_mask(tx_chan, &free_m2m_id_mask);
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m2m_trigger.instance_id = __builtin_ctz(free_m2m_id_mask);
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TEST_ESP_OK(gdma_connect(tx_chan, m2m_trigger));
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uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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TEST_ASSERT_NOT_NULL(src_buf);
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dma_descriptor_align8_t *tx_descs = (dma_descriptor_align8_t *) src_buf;
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uint8_t *src_data = src_buf + 64;
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memcpy(src_data, test_input_string, input_data_size);
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tx_descs->buffer = src_data;
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tx_descs->dw0.size = 256 - 64;
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tx_descs->dw0.length = input_data_size;
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tx_descs->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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tx_descs->dw0.suc_eof = 1;
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tx_descs->next = NULL;
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#if CONFIG_IDF_TARGET_ESP32P4
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// do write-back for the buffer because it's in the cache
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Cache_WriteBack_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)src_buf, 256);
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#endif
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for (int i = 0; i < test_num_crc_algorithm; i++) {
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gdma_crc_calculator_config_t crc_config = {
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.crc_bit_width = crc_test_cases[i].crc_bit_width,
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.init_value = crc_test_cases[i].init_value,
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.poly_hex = crc_test_cases[i].poly_hex,
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.reverse_data_mask = crc_test_cases[i].reverse_data_mask,
|
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};
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TEST_ESP_OK(gdma_config_crc_calculator(tx_chan, &crc_config));
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TEST_ESP_OK(gdma_reset(tx_chan));
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TEST_ESP_OK(gdma_start(tx_chan, (intptr_t)tx_descs));
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|
// simply wait for the transfer done
|
|
vTaskDelay(pdMS_TO_TICKS(100));
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TEST_ESP_OK(gdma_crc_get_result(tx_chan, &crc_result));
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printf("CRC Result: 0x%"PRIx32"\r\n", crc_result);
|
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TEST_ASSERT_EQUAL(crc_test_cases[i].expected_result, crc_result);
|
|
}
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|
|
|
free(src_buf);
|
|
}
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|
|
|
TEST_CASE("GDMA CRC Calculation", "[GDMA]")
|
|
{
|
|
gdma_channel_handle_t tx_chan = NULL;
|
|
gdma_channel_alloc_config_t tx_chan_alloc_config = {
|
|
.direction = GDMA_CHANNEL_DIRECTION_TX,
|
|
};
|
|
#if SOC_AHB_GDMA_SUPPORTED
|
|
printf("Test CRC calculation for AHB GDMA\r\n");
|
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TEST_ESP_OK(gdma_new_ahb_channel(&tx_chan_alloc_config, &tx_chan));
|
|
test_gdma_crc_calculation(tx_chan, 4);
|
|
TEST_ESP_OK(gdma_del_channel(tx_chan));
|
|
#endif // SOC_AHB_GDMA_SUPPORTED
|
|
|
|
#if SOC_AXI_GDMA_SUPPORTED
|
|
printf("Test CRC calculation for AXI GDMA\r\n");
|
|
TEST_ESP_OK(gdma_new_axi_channel(&tx_chan_alloc_config, &tx_chan));
|
|
test_gdma_crc_calculation(tx_chan, 3);
|
|
TEST_ESP_OK(gdma_del_channel(tx_chan));
|
|
#endif // SOC_AXI_GDMA_SUPPORTED
|
|
}
|
|
#endif // SOC_GDMA_SUPPORT_CRC
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