kopia lustrzana https://github.com/espressif/esp-idf
300 wiersze
9.0 KiB
C
300 wiersze
9.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <assert.h>
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#include "string.h"
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "esp32s3/rom/spi_flash.h"
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#include "soc/efuse_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/soc_caps.h"
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#include "flash_qio_mode.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_flash_priv.h"
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#include "bootloader_common.h"
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#include "bootloader_flash.h"
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#include "bootloader_init.h"
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#include "hal/mmu_hal.h"
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#include "hal/mmu_ll.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_ll.h"
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#define FLASH_IO_MATRIX_DUMMY_40M 0
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#define FLASH_IO_MATRIX_DUMMY_80M 0
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#define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM 3
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#define FLASH_CS_SETUP_TIME 3
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#define FLASH_CS_HOLD_TIME 3
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#define FLASH_CS_HOLD_DELAY 2
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void bootloader_flash_update_id()
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{
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esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
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chip->device_id = bootloader_read_flash_id();
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}
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void IRAM_ATTR bootloader_flash_cs_timing_config()
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{
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//SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time, cs_hold_delay registers for FLASH, so we only need to set SPI0 related registers here
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if (bootloader_flash_is_octal_mode_enabled()) {
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SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, FLASH_CS_HOLD_TIME, SPI_MEM_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, FLASH_CS_SETUP_TIME, SPI_MEM_CS_SETUP_TIME_S);
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//CS high time
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_DELAY_V, FLASH_CS_HOLD_DELAY, SPI_MEM_CS_HOLD_DELAY_S);
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} else {
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
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SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
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}
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}
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void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
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{
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uint32_t spi_clk_div = 0;
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switch (pfhdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_DIV_1:
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spi_clk_div = 1;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_2:
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spi_clk_div = 2;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_3:
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spi_clk_div = 3;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_4:
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spi_clk_div = 4;
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break;
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default:
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break;
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}
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esp_rom_spiflash_config_clk(spi_clk_div, 0);
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esp_rom_spiflash_config_clk(spi_clk_div, 1);
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}
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void IRAM_ATTR bootloader_flash_set_dummy_out(void)
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{
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REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
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REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
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}
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void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr)
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{
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bootloader_configure_spi_pins(1);
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bootloader_flash_set_dummy_out();
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}
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static const char *TAG = "boot.esp32s3";
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void IRAM_ATTR bootloader_configure_spi_pins(int drv)
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{
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
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uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
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uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
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uint8_t d_gpio_num = SPI_D_GPIO_NUM;
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uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
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uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
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uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
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if (spiconfig == 0) {
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} else {
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clk_gpio_num = spiconfig & 0x3f;
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q_gpio_num = (spiconfig >> 6) & 0x3f;
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d_gpio_num = (spiconfig >> 12) & 0x3f;
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cs0_gpio_num = (spiconfig >> 18) & 0x3f;
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hd_gpio_num = (spiconfig >> 24) & 0x3f;
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wp_gpio_num = wp_pin;
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}
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esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
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if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
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esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
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}
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if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
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esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
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}
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}
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static void update_flash_config(const esp_image_header_t *bootloader_hdr)
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{
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uint32_t size;
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switch (bootloader_hdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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size = 1;
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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size = 2;
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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size = 4;
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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size = 8;
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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size = 16;
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break;
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case ESP_IMAGE_FLASH_SIZE_32MB:
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size = 32;
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break;
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case ESP_IMAGE_FLASH_SIZE_64MB:
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size = 64;
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break;
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case ESP_IMAGE_FLASH_SIZE_128MB:
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size = 128;
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break;
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default:
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size = 2;
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}
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cache_hal_disable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
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// Set flash chip size
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esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
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// TODO: set mode
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// TODO: set frequency
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cache_hal_enable(CACHE_TYPE_ALL, CACHE_LL_LEVEL_EXT_MEM);
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}
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static void print_flash_info(const esp_image_header_t *bootloader_hdr)
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{
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ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
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ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
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ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
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ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
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ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
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const char *str;
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switch (bootloader_hdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_DIV_2:
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str = "40MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_3:
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str = "26.7MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_4:
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str = "20MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_1:
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str = "80MHz";
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break;
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default:
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str = "20MHz";
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break;
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}
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ESP_EARLY_LOGI(TAG, "Boot SPI Speed : %s", str);
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/* SPI mode could have been set to QIO during boot already,
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so test the SPI registers not the flash header */
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esp_rom_spiflash_read_mode_t spi_mode = bootloader_flash_get_spi_mode();
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switch (spi_mode) {
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case ESP_ROM_SPIFLASH_QIO_MODE:
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str = "QIO";
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break;
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case ESP_ROM_SPIFLASH_QOUT_MODE:
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str = "QOUT";
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break;
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case ESP_ROM_SPIFLASH_DIO_MODE:
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str = "DIO";
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break;
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case ESP_ROM_SPIFLASH_DOUT_MODE:
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str = "DOUT";
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break;
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case ESP_ROM_SPIFLASH_FASTRD_MODE:
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str = "FAST READ";
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break;
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default:
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str = "SLOW READ";
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break;
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}
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ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str);
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switch (bootloader_hdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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str = "1MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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str = "2MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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str = "4MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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str = "8MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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str = "16MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_32MB:
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str = "32MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_64MB:
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str = "64MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_128MB:
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str = "128MB";
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break;
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default:
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str = "2MB";
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break;
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}
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ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
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}
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static void IRAM_ATTR bootloader_init_flash_configure(void)
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{
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bootloader_flash_dummy_config(&bootloader_image_hdr);
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bootloader_flash_cs_timing_config();
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}
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static void bootloader_spi_flash_resume(void)
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{
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bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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}
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esp_err_t bootloader_init_spi_flash(void)
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{
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bootloader_init_flash_configure();
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#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
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ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
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return ESP_FAIL;
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}
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#endif
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#if CONFIG_SPI_FLASH_HPM_ENABLE
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// Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot.
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bootloader_spi_flash_reset();
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#endif
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bootloader_spi_flash_resume();
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bootloader_flash_unlock();
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
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if (!bootloader_flash_is_octal_mode_enabled()) {
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bootloader_enable_qio_mode();
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}
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#endif
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#if CONFIG_SPI_FLASH_32BIT_ADDR_ENABLE
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bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
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#endif
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print_flash_info(&bootloader_image_hdr);
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update_flash_config(&bootloader_image_hdr);
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//ensure the flash is write-protected
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bootloader_enable_wp();
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return ESP_OK;
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}
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