kopia lustrzana https://github.com/espressif/esp-idf
378 wiersze
16 KiB
C
378 wiersze
16 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** PMS_LP_PERI_PMS_DATE_REG register
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* Version control register
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*/
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#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
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/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
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* Version control register
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*/
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#define PMS_LP_PERI_PMS_DATE 0xFFFFFFFFU
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#define PMS_LP_PERI_PMS_DATE_M (PMS_LP_PERI_PMS_DATE_V << PMS_LP_PERI_PMS_DATE_S)
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#define PMS_LP_PERI_PMS_DATE_V 0xFFFFFFFFU
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#define PMS_LP_PERI_PMS_DATE_S 0
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/** PMS_LP_PERI_PMS_CLK_EN_REG register
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* Clock gating register
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*/
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#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
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/** PMS_LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
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* Configures whether to keep the clock always on.
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* 0: Enable automatic clock gating
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* 1: Keep the clock always on
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*/
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#define PMS_LP_PERI_PMS_CLK_EN (BIT(0))
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#define PMS_LP_PERI_PMS_CLK_EN_M (PMS_LP_PERI_PMS_CLK_EN_V << PMS_LP_PERI_PMS_CLK_EN_S)
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#define PMS_LP_PERI_PMS_CLK_EN_V 0x00000001U
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#define PMS_LP_PERI_PMS_CLK_EN_S 0
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/** PMS_LP_MM_LP_PERI_PMS_REG0_REG register
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* Permission control register0 for LP CPU in machine mode
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*/
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#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
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/** PMS_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP system
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* registers.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_SYSREG_ALLOW (BIT(0))
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#define PMS_LP_MM_LP_SYSREG_ALLOW_M (PMS_LP_MM_LP_SYSREG_ALLOW_V << PMS_LP_MM_LP_SYSREG_ALLOW_S)
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#define PMS_LP_MM_LP_SYSREG_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_SYSREG_ALLOW_S 0
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/** PMS_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP
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* always-on clock and reset).
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_AONCLKRST_ALLOW (BIT(1))
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#define PMS_LP_MM_LP_AONCLKRST_ALLOW_M (PMS_LP_MM_LP_AONCLKRST_ALLOW_V << PMS_LP_MM_LP_AONCLKRST_ALLOW_S)
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#define PMS_LP_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_AONCLKRST_ALLOW_S 1
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/** PMS_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP timer.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_TIMER_ALLOW (BIT(2))
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#define PMS_LP_MM_LP_TIMER_ALLOW_M (PMS_LP_MM_LP_TIMER_ALLOW_V << PMS_LP_MM_LP_TIMER_ALLOW_S)
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#define PMS_LP_MM_LP_TIMER_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_TIMER_ALLOW_S 2
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/** PMS_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP ANAPERI
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* (analog peripherals).
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_ANAPERI_ALLOW (BIT(3))
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#define PMS_LP_MM_LP_ANAPERI_ALLOW_M (PMS_LP_MM_LP_ANAPERI_ALLOW_V << PMS_LP_MM_LP_ANAPERI_ALLOW_S)
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#define PMS_LP_MM_LP_ANAPERI_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_ANAPERI_ALLOW_S 3
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/** PMS_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP PMU (Power
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* Management Unit).
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_PMU_ALLOW (BIT(4))
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#define PMS_LP_MM_LP_PMU_ALLOW_M (PMS_LP_MM_LP_PMU_ALLOW_V << PMS_LP_MM_LP_PMU_ALLOW_S)
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#define PMS_LP_MM_LP_PMU_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_PMU_ALLOW_S 4
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/** PMS_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog
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* timer).
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_WDT_ALLOW (BIT(5))
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#define PMS_LP_MM_LP_WDT_ALLOW_M (PMS_LP_MM_LP_WDT_ALLOW_V << PMS_LP_MM_LP_WDT_ALLOW_S)
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#define PMS_LP_MM_LP_WDT_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_WDT_ALLOW_S 5
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/** PMS_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP Mailbox
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* Controller.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_MAILBOX_ALLOW (BIT(6))
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#define PMS_LP_MM_LP_MAILBOX_ALLOW_M (PMS_LP_MM_LP_MAILBOX_ALLOW_V << PMS_LP_MM_LP_MAILBOX_ALLOW_S)
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#define PMS_LP_MM_LP_MAILBOX_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_MAILBOX_ALLOW_S 6
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/** PMS_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP RTC.
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* 0: Not allowed
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* 1: Allow
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*/
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#define PMS_LP_MM_LP_RTC_ALLOW (BIT(7))
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#define PMS_LP_MM_LP_RTC_ALLOW_M (PMS_LP_MM_LP_RTC_ALLOW_V << PMS_LP_MM_LP_RTC_ALLOW_S)
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#define PMS_LP_MM_LP_RTC_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_RTC_ALLOW_S 7
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/** PMS_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP PREICLKRST
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* (peripheral clock and reset).
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_PERICLKRST_ALLOW (BIT(8))
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#define PMS_LP_MM_LP_PERICLKRST_ALLOW_M (PMS_LP_MM_LP_PERICLKRST_ALLOW_V << PMS_LP_MM_LP_PERICLKRST_ALLOW_S)
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#define PMS_LP_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_PERICLKRST_ALLOW_S 8
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/** PMS_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP UART.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_UART_ALLOW (BIT(9))
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#define PMS_LP_MM_LP_UART_ALLOW_M (PMS_LP_MM_LP_UART_ALLOW_V << PMS_LP_MM_LP_UART_ALLOW_S)
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#define PMS_LP_MM_LP_UART_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_UART_ALLOW_S 9
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/** PMS_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP I2S.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_I2C_ALLOW (BIT(10))
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#define PMS_LP_MM_LP_I2C_ALLOW_M (PMS_LP_MM_LP_I2C_ALLOW_V << PMS_LP_MM_LP_I2C_ALLOW_S)
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#define PMS_LP_MM_LP_I2C_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_I2C_ALLOW_S 10
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/** PMS_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP SPI.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_SPI_ALLOW (BIT(11))
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#define PMS_LP_MM_LP_SPI_ALLOW_M (PMS_LP_MM_LP_SPI_ALLOW_V << PMS_LP_MM_LP_SPI_ALLOW_S)
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#define PMS_LP_MM_LP_SPI_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_SPI_ALLOW_S 11
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/** PMS_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP I2C master.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_I2CMST_ALLOW (BIT(12))
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#define PMS_LP_MM_LP_I2CMST_ALLOW_M (PMS_LP_MM_LP_I2CMST_ALLOW_V << PMS_LP_MM_LP_I2CMST_ALLOW_S)
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#define PMS_LP_MM_LP_I2CMST_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_I2CMST_ALLOW_S 12
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/** PMS_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP I2S.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_I2S_ALLOW (BIT(13))
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#define PMS_LP_MM_LP_I2S_ALLOW_M (PMS_LP_MM_LP_I2S_ALLOW_V << PMS_LP_MM_LP_I2S_ALLOW_S)
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#define PMS_LP_MM_LP_I2S_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_I2S_ALLOW_S 13
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/** PMS_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP ADC.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_ADC_ALLOW (BIT(14))
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#define PMS_LP_MM_LP_ADC_ALLOW_M (PMS_LP_MM_LP_ADC_ALLOW_V << PMS_LP_MM_LP_ADC_ALLOW_S)
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#define PMS_LP_MM_LP_ADC_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_ADC_ALLOW_S 14
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/** PMS_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP touch sensor.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_TOUCH_ALLOW (BIT(15))
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#define PMS_LP_MM_LP_TOUCH_ALLOW_M (PMS_LP_MM_LP_TOUCH_ALLOW_V << PMS_LP_MM_LP_TOUCH_ALLOW_S)
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#define PMS_LP_MM_LP_TOUCH_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_TOUCH_ALLOW_S 15
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/** PMS_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP IO MUX.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_IOMUX_ALLOW (BIT(16))
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#define PMS_LP_MM_LP_IOMUX_ALLOW_M (PMS_LP_MM_LP_IOMUX_ALLOW_V << PMS_LP_MM_LP_IOMUX_ALLOW_S)
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#define PMS_LP_MM_LP_IOMUX_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_IOMUX_ALLOW_S 16
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/** PMS_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP INTR
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* (interrupt).
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_INTR_ALLOW (BIT(17))
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#define PMS_LP_MM_LP_INTR_ALLOW_M (PMS_LP_MM_LP_INTR_ALLOW_V << PMS_LP_MM_LP_INTR_ALLOW_S)
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#define PMS_LP_MM_LP_INTR_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_INTR_ALLOW_S 17
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/** PMS_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP eFuse.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_EFUSE_ALLOW (BIT(18))
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#define PMS_LP_MM_LP_EFUSE_ALLOW_M (PMS_LP_MM_LP_EFUSE_ALLOW_V << PMS_LP_MM_LP_EFUSE_ALLOW_S)
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#define PMS_LP_MM_LP_EFUSE_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_EFUSE_ALLOW_S 18
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/** PMS_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_PMS_ALLOW (BIT(19))
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#define PMS_LP_MM_LP_PMS_ALLOW_M (PMS_LP_MM_LP_PMS_ALLOW_V << PMS_LP_MM_LP_PMS_ALLOW_S)
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#define PMS_LP_MM_LP_PMS_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_PMS_ALLOW_S 19
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/** PMS_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access
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* HP2LP_PERI_PMS_REG.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_HP2LP_PMS_ALLOW (BIT(20))
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#define PMS_LP_MM_HP2LP_PMS_ALLOW_M (PMS_LP_MM_HP2LP_PMS_ALLOW_V << PMS_LP_MM_HP2LP_PMS_ALLOW_S)
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#define PMS_LP_MM_HP2LP_PMS_ALLOW_V 0x00000001U
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#define PMS_LP_MM_HP2LP_PMS_ALLOW_S 20
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/** PMS_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP temperature
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* sensor.
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_TSENS_ALLOW (BIT(21))
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#define PMS_LP_MM_LP_TSENS_ALLOW_M (PMS_LP_MM_LP_TSENS_ALLOW_V << PMS_LP_MM_LP_TSENS_ALLOW_S)
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#define PMS_LP_MM_LP_TSENS_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_TSENS_ALLOW_S 21
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/** PMS_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware
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* Unique Key).
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* 0: Not allowed
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* 1: Allowed
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*/
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#define PMS_LP_MM_LP_HUK_ALLOW (BIT(22))
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#define PMS_LP_MM_LP_HUK_ALLOW_M (PMS_LP_MM_LP_HUK_ALLOW_V << PMS_LP_MM_LP_HUK_ALLOW_S)
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#define PMS_LP_MM_LP_HUK_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_HUK_ALLOW_S 22
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/** PMS_LP_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP SRAM.
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* 0: Not allowed
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* 1: Allow
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*/
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#define PMS_LP_MM_LP_SRAM_ALLOW (BIT(23))
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#define PMS_LP_MM_LP_SRAM_ALLOW_M (PMS_LP_MM_LP_SRAM_ALLOW_V << PMS_LP_MM_LP_SRAM_ALLOW_S)
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#define PMS_LP_MM_LP_SRAM_ALLOW_V 0x00000001U
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#define PMS_LP_MM_LP_SRAM_ALLOW_S 23
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/** PMS_PERI_REGION0_LOW_REG register
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* Region0 start address configuration register
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*/
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#define PMS_PERI_REGION0_LOW_REG (DR_REG_PMS_BASE + 0xc)
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/** PMS_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
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* Configures the high 30 bits of the start address of peripheral register's region0.
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*/
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#define PMS_PERI_REGION0_LOW 0x3FFFFFFFU
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#define PMS_PERI_REGION0_LOW_M (PMS_PERI_REGION0_LOW_V << PMS_PERI_REGION0_LOW_S)
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#define PMS_PERI_REGION0_LOW_V 0x3FFFFFFFU
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#define PMS_PERI_REGION0_LOW_S 2
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/** PMS_PERI_REGION0_HIGH_REG register
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* Region0 end address configuration register
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*/
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#define PMS_PERI_REGION0_HIGH_REG (DR_REG_PMS_BASE + 0x10)
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/** PMS_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
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* Configures the high 30 bits of the end address of peripheral register's region0.
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*/
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#define PMS_PERI_REGION0_HIGH 0x3FFFFFFFU
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#define PMS_PERI_REGION0_HIGH_M (PMS_PERI_REGION0_HIGH_V << PMS_PERI_REGION0_HIGH_S)
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#define PMS_PERI_REGION0_HIGH_V 0x3FFFFFFFU
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#define PMS_PERI_REGION0_HIGH_S 2
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/** PMS_PERI_REGION1_LOW_REG register
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* Region1 start address configuration register
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*/
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#define PMS_PERI_REGION1_LOW_REG (DR_REG_PMS_BASE + 0x14)
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/** PMS_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
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* Configures the high 30 bits of the start address of peripheral register's region1.
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*/
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#define PMS_PERI_REGION1_LOW 0x3FFFFFFFU
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#define PMS_PERI_REGION1_LOW_M (PMS_PERI_REGION1_LOW_V << PMS_PERI_REGION1_LOW_S)
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#define PMS_PERI_REGION1_LOW_V 0x3FFFFFFFU
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#define PMS_PERI_REGION1_LOW_S 2
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/** PMS_PERI_REGION1_HIGH_REG register
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* Region1 end address configuration register
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*/
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#define PMS_PERI_REGION1_HIGH_REG (DR_REG_PMS_BASE + 0x18)
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/** PMS_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
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* Configures the high 30 bits of the end address of peripheral register's region1.
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*/
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#define PMS_PERI_REGION1_HIGH 0x3FFFFFFFU
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#define PMS_PERI_REGION1_HIGH_M (PMS_PERI_REGION1_HIGH_V << PMS_PERI_REGION1_HIGH_S)
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#define PMS_PERI_REGION1_HIGH_V 0x3FFFFFFFU
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#define PMS_PERI_REGION1_HIGH_S 2
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/** PMS_PERI_REGION_PMS_REG register
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* Permission register of region
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*/
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#define PMS_PERI_REGION_PMS_REG (DR_REG_PMS_BASE + 0x1c)
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/** PMS_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
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* Configures whether LP core in machine mode has permission to access address region0
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* and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.
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* 0: Not allowed
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* 1: Allow
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*/
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#define PMS_LP_CORE_REGION_PMS 0x00000003U
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#define PMS_LP_CORE_REGION_PMS_M (PMS_LP_CORE_REGION_PMS_V << PMS_LP_CORE_REGION_PMS_S)
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#define PMS_LP_CORE_REGION_PMS_V 0x00000003U
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#define PMS_LP_CORE_REGION_PMS_S 0
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/** PMS_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
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* Configures whether HP CPU0 in user mode has permission to access address region0
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* and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1.
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* 0: Not allowed
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* 1: Allow
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*/
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#define PMS_HP_CORE0_UM_REGION_PMS 0x00000003U
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#define PMS_HP_CORE0_UM_REGION_PMS_M (PMS_HP_CORE0_UM_REGION_PMS_V << PMS_HP_CORE0_UM_REGION_PMS_S)
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#define PMS_HP_CORE0_UM_REGION_PMS_V 0x00000003U
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#define PMS_HP_CORE0_UM_REGION_PMS_S 2
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/** PMS_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
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* Configures whether HP CPU0 in machine mode has permission to access address region0
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* and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1.
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* 0: Not allowed
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* 1: Allow
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*/
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#define PMS_HP_CORE0_MM_REGION_PMS 0x00000003U
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#define PMS_HP_CORE0_MM_REGION_PMS_M (PMS_HP_CORE0_MM_REGION_PMS_V << PMS_HP_CORE0_MM_REGION_PMS_S)
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#define PMS_HP_CORE0_MM_REGION_PMS_V 0x00000003U
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#define PMS_HP_CORE0_MM_REGION_PMS_S 4
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/** PMS_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
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* Configures whether HP CPU1 in user mode has permission to access address region0
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* and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1.
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* 0: Not allowed
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* 1: Allow
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*/
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#define PMS_HP_CORE1_UM_REGION_PMS 0x00000003U
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#define PMS_HP_CORE1_UM_REGION_PMS_M (PMS_HP_CORE1_UM_REGION_PMS_V << PMS_HP_CORE1_UM_REGION_PMS_S)
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#define PMS_HP_CORE1_UM_REGION_PMS_V 0x00000003U
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#define PMS_HP_CORE1_UM_REGION_PMS_S 6
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/** PMS_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
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* Configures whether HP CPU1 in machine mode has permission to access address region0
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* and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1.
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* 0: Not allowed
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* 1: Allow
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*/
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#define PMS_HP_CORE1_MM_REGION_PMS 0x00000003U
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#define PMS_HP_CORE1_MM_REGION_PMS_M (PMS_HP_CORE1_MM_REGION_PMS_V << PMS_HP_CORE1_MM_REGION_PMS_S)
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#define PMS_HP_CORE1_MM_REGION_PMS_V 0x00000003U
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#define PMS_HP_CORE1_MM_REGION_PMS_S 8
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#ifdef __cplusplus
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}
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#endif
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