kopia lustrzana https://github.com/espressif/esp-idf
563 wiersze
21 KiB
C
563 wiersze
21 KiB
C
/**
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
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/** TIMG_T0CONFIG_REG register
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* Timer 0 configuration register
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*/
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#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
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/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
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* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
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* clock of timer group.
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*/
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#define TIMG_T0_USE_XTAL (BIT(9))
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#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
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#define TIMG_T0_USE_XTAL_V 0x00000001U
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#define TIMG_T0_USE_XTAL_S 9
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/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
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* When set, the alarm is enabled. This bit is automatically cleared once an
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* alarm occurs.
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*/
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#define TIMG_T0_ALARM_EN (BIT(10))
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#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
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#define TIMG_T0_ALARM_EN_V 0x00000001U
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#define TIMG_T0_ALARM_EN_S 10
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/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
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* When set, Timer 0 's clock divider counter will be reset.
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*/
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#define TIMG_T0_DIVCNT_RST (BIT(12))
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#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
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#define TIMG_T0_DIVCNT_RST_V 0x00000001U
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#define TIMG_T0_DIVCNT_RST_S 12
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/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
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* Timer 0 clock (T0_clk) prescaler value.
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*/
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#define TIMG_T0_DIVIDER 0x0000FFFFU
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#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
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#define TIMG_T0_DIVIDER_V 0x0000FFFFU
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#define TIMG_T0_DIVIDER_S 13
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/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
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* When set, timer 0 auto-reload at alarm is enabled.
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*/
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#define TIMG_T0_AUTORELOAD (BIT(29))
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#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
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#define TIMG_T0_AUTORELOAD_V 0x00000001U
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#define TIMG_T0_AUTORELOAD_S 29
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/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
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* When set, the timer 0 time-base counter will increment every clock tick. When
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* cleared, the timer 0 time-base counter will decrement.
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*/
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#define TIMG_T0_INCREASE (BIT(30))
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#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
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#define TIMG_T0_INCREASE_V 0x00000001U
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#define TIMG_T0_INCREASE_S 30
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/** TIMG_T0_EN : R/W; bitpos: [31]; default: 0;
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* When set, the timer 0 time-base counter is enabled.
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*/
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#define TIMG_T0_EN (BIT(31))
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#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
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#define TIMG_T0_EN_V 0x00000001U
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#define TIMG_T0_EN_S 31
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/** TIMG_T0LO_REG register
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* Timer 0 current value, low 32 bits
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*/
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#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
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/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
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* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
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* of timer 0 can be read here.
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*/
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#define TIMG_T0_LO 0xFFFFFFFFU
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#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
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#define TIMG_T0_LO_V 0xFFFFFFFFU
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#define TIMG_T0_LO_S 0
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/** TIMG_T0HI_REG register
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* Timer $x current value, high 22 bits
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*/
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#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
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/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
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* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
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* of timer $x can be read here.
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*/
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#define TIMG_T0_HI 0x003FFFFFU
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#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
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#define TIMG_T0_HI_V 0x003FFFFFU
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#define TIMG_T0_HI_S 0
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/** TIMG_T0UPDATE_REG register
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* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
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*/
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#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
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/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
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* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
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*/
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#define TIMG_T0_UPDATE (BIT(31))
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#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
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#define TIMG_T0_UPDATE_V 0x00000001U
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#define TIMG_T0_UPDATE_S 31
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/** TIMG_T0ALARMLO_REG register
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* Timer $x alarm value, low 32 bits
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*/
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#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
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/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
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* Timer $x alarm trigger time-base counter value, low 32 bits.
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*/
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#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
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#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
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#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
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#define TIMG_T0_ALARM_LO_S 0
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/** TIMG_T0ALARMHI_REG register
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* Timer $x alarm value, high bits
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*/
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#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
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/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
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* Timer $x alarm trigger time-base counter value, high 22 bits.
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*/
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#define TIMG_T0_ALARM_HI 0x003FFFFFU
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#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
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#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
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#define TIMG_T0_ALARM_HI_S 0
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/** TIMG_T0LOADLO_REG register
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* Timer $x reload value, low 32 bits
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*/
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#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
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/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
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* Low 32 bits of the value that a reload will load onto timer $x time-base
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* Counter.
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*/
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#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
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#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
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#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
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#define TIMG_T0_LOAD_LO_S 0
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/** TIMG_T0LOADHI_REG register
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* Timer $x reload value, high 22 bits
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*/
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#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
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/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
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* High 22 bits of the value that a reload will load onto timer $x time-base
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* counter.
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*/
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#define TIMG_T0_LOAD_HI 0x003FFFFFU
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#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
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#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
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#define TIMG_T0_LOAD_HI_S 0
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/** TIMG_T0LOAD_REG register
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* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
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*/
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#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
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/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
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*
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* Write any value to trigger a timer $x time-base counter reload.
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*/
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#define TIMG_T0_LOAD 0xFFFFFFFFU
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#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
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#define TIMG_T0_LOAD_V 0xFFFFFFFFU
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#define TIMG_T0_LOAD_S 0
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/** TIMG_WDTCONFIG0_REG register
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* Watchdog timer configuration register
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*/
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#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
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/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
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* WDT reset CPU enable.
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*/
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#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
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#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
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#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
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#define TIMG_WDT_APPCPU_RESET_EN_S 12
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/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
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* WDT reset CPU enable.
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*/
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#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
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#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
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#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
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#define TIMG_WDT_PROCPU_RESET_EN_S 13
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/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
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* When set, Flash boot protection is enabled.
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*/
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#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
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#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
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#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
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#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
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/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
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* System reset signal length selection. 0: 100 ns, 1: 200 ns,
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* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
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*/
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#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
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#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
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#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
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#define TIMG_WDT_SYS_RESET_LENGTH_S 15
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/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
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* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
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* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
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*/
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#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
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#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
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#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
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#define TIMG_WDT_CPU_RESET_LENGTH_S 18
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/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0;
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* choose WDT clock:0-apb_clk; 1-xtal_clk.
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*/
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#define TIMG_WDT_USE_XTAL (BIT(21))
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#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S)
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#define TIMG_WDT_USE_XTAL_V 0x00000001U
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#define TIMG_WDT_USE_XTAL_S 21
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/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
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* update the WDT configuration registers
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*/
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#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
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#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
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#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
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#define TIMG_WDT_CONF_UPDATE_EN_S 22
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/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
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* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
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*/
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#define TIMG_WDT_STG3 0x00000003U
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#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
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#define TIMG_WDT_STG3_V 0x00000003U
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#define TIMG_WDT_STG3_S 23
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/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
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* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
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*/
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#define TIMG_WDT_STG2 0x00000003U
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#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
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#define TIMG_WDT_STG2_V 0x00000003U
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#define TIMG_WDT_STG2_S 25
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/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
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* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
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*/
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#define TIMG_WDT_STG1 0x00000003U
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#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
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#define TIMG_WDT_STG1_V 0x00000003U
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#define TIMG_WDT_STG1_S 27
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/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
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* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
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*/
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#define TIMG_WDT_STG0 0x00000003U
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#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
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#define TIMG_WDT_STG0_V 0x00000003U
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#define TIMG_WDT_STG0_S 29
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/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
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* When set, MWDT is enabled.
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*/
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#define TIMG_WDT_EN (BIT(31))
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#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
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#define TIMG_WDT_EN_V 0x00000001U
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#define TIMG_WDT_EN_S 31
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/** TIMG_WDTCONFIG1_REG register
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* Watchdog timer prescaler register
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*/
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#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
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/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
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* When set, WDT 's clock divider counter will be reset.
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*/
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#define TIMG_WDT_DIVCNT_RST (BIT(0))
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#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
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#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
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#define TIMG_WDT_DIVCNT_RST_S 0
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/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
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* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
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* TIMG_WDT_CLK_PRESCALE.
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*/
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#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
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#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
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#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
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#define TIMG_WDT_CLK_PRESCALE_S 16
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/** TIMG_WDTCONFIG2_REG register
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* Watchdog timer stage 0 timeout value
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*/
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#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
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/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
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* Stage 0 timeout value, in MWDT clock cycles.
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*/
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#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
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#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
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#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
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#define TIMG_WDT_STG0_HOLD_S 0
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/** TIMG_WDTCONFIG3_REG register
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* Watchdog timer stage 1 timeout value
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*/
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#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
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/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
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* Stage 1 timeout value, in MWDT clock cycles.
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*/
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#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
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#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
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#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
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#define TIMG_WDT_STG1_HOLD_S 0
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/** TIMG_WDTCONFIG4_REG register
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* Watchdog timer stage 2 timeout value
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*/
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#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
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/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
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* Stage 2 timeout value, in MWDT clock cycles.
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*/
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#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
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#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
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#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
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#define TIMG_WDT_STG2_HOLD_S 0
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/** TIMG_WDTCONFIG5_REG register
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* Watchdog timer stage 3 timeout value
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*/
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#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
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/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
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* Stage 3 timeout value, in MWDT clock cycles.
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*/
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#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
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#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
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#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
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#define TIMG_WDT_STG3_HOLD_S 0
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/** TIMG_WDTFEED_REG register
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* Write to feed the watchdog timer
|
|
*/
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#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
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/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
|
|
* Write any value to feed the MWDT. (WO)
|
|
*/
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#define TIMG_WDT_FEED 0xFFFFFFFFU
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#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
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#define TIMG_WDT_FEED_V 0xFFFFFFFFU
|
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#define TIMG_WDT_FEED_S 0
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|
|
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/** TIMG_WDTWPROTECT_REG register
|
|
* Watchdog write protect register
|
|
*/
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#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
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/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
|
|
* If the register contains a different value than its reset value, write
|
|
* protection is enabled.
|
|
*/
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#define TIMG_WDT_WKEY 0xFFFFFFFFU
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#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
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#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
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#define TIMG_WDT_WKEY_S 0
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/** TIMG_RTCCALICFG_REG register
|
|
* RTC calibration configure register
|
|
*/
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#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
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/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
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* Reserved
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|
*/
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#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
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#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
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#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
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#define TIMG_RTC_CALI_START_CYCLING_S 12
|
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/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1;
|
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* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
|
|
*/
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#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
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#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
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#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
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#define TIMG_RTC_CALI_CLK_SEL_S 13
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/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
|
|
* Reserved
|
|
*/
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|
#define TIMG_RTC_CALI_RDY (BIT(15))
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|
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
|
|
#define TIMG_RTC_CALI_RDY_V 0x00000001U
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|
#define TIMG_RTC_CALI_RDY_S 15
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|
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
|
|
* Reserved
|
|
*/
|
|
#define TIMG_RTC_CALI_MAX 0x00007FFFU
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|
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
|
|
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
|
|
#define TIMG_RTC_CALI_MAX_S 16
|
|
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
|
|
* Reserved
|
|
*/
|
|
#define TIMG_RTC_CALI_START (BIT(31))
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|
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
|
|
#define TIMG_RTC_CALI_START_V 0x00000001U
|
|
#define TIMG_RTC_CALI_START_S 31
|
|
|
|
/** TIMG_RTCCALICFG1_REG register
|
|
* RTC calibration configure1 register
|
|
*/
|
|
#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
|
|
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
|
|
* Reserved
|
|
*/
|
|
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
|
|
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
|
|
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
|
|
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
|
|
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
|
|
* Reserved
|
|
*/
|
|
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
|
|
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
|
|
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
|
|
#define TIMG_RTC_CALI_VALUE_S 7
|
|
|
|
/** TIMG_INT_ENA_TIMERS_REG register
|
|
* Interrupt enable bits
|
|
*/
|
|
#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
|
|
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
|
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
|
*/
|
|
#define TIMG_T0_INT_ENA (BIT(0))
|
|
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
|
|
#define TIMG_T0_INT_ENA_V 0x00000001U
|
|
#define TIMG_T0_INT_ENA_S 0
|
|
/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0;
|
|
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
|
*/
|
|
#define TIMG_WDT_INT_ENA (BIT(1))
|
|
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
|
|
#define TIMG_WDT_INT_ENA_V 0x00000001U
|
|
#define TIMG_WDT_INT_ENA_S 1
|
|
|
|
/** TIMG_INT_RAW_TIMERS_REG register
|
|
* Raw interrupt status
|
|
*/
|
|
#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
|
|
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
|
|
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
|
*/
|
|
#define TIMG_T0_INT_RAW (BIT(0))
|
|
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
|
|
#define TIMG_T0_INT_RAW_V 0x00000001U
|
|
#define TIMG_T0_INT_RAW_S 0
|
|
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
|
|
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
|
*/
|
|
#define TIMG_WDT_INT_RAW (BIT(1))
|
|
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
|
|
#define TIMG_WDT_INT_RAW_V 0x00000001U
|
|
#define TIMG_WDT_INT_RAW_S 1
|
|
|
|
/** TIMG_INT_ST_TIMERS_REG register
|
|
* Masked interrupt status
|
|
*/
|
|
#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
|
|
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
|
|
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
|
*/
|
|
#define TIMG_T0_INT_ST (BIT(0))
|
|
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
|
|
#define TIMG_T0_INT_ST_V 0x00000001U
|
|
#define TIMG_T0_INT_ST_S 0
|
|
/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0;
|
|
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
|
*/
|
|
#define TIMG_WDT_INT_ST (BIT(1))
|
|
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
|
|
#define TIMG_WDT_INT_ST_V 0x00000001U
|
|
#define TIMG_WDT_INT_ST_S 1
|
|
|
|
/** TIMG_INT_CLR_TIMERS_REG register
|
|
* Interrupt clear bits
|
|
*/
|
|
#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
|
|
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
|
|
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
|
*/
|
|
#define TIMG_T0_INT_CLR (BIT(0))
|
|
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
|
|
#define TIMG_T0_INT_CLR_V 0x00000001U
|
|
#define TIMG_T0_INT_CLR_S 0
|
|
/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0;
|
|
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
|
*/
|
|
#define TIMG_WDT_INT_CLR (BIT(1))
|
|
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
|
|
#define TIMG_WDT_INT_CLR_V 0x00000001U
|
|
#define TIMG_WDT_INT_CLR_S 1
|
|
|
|
/** TIMG_RTCCALICFG2_REG register
|
|
* Timer group calibration register
|
|
*/
|
|
#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
|
|
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
|
|
* RTC calibration timeout indicator
|
|
*/
|
|
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
|
|
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
|
|
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
|
|
#define TIMG_RTC_CALI_TIMEOUT_S 0
|
|
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
|
|
* Cycles that release calibration timeout reset
|
|
*/
|
|
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
|
|
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
|
|
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
|
|
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
|
|
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
|
|
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
|
* exceeds this threshold, a timeout is triggered.
|
|
*/
|
|
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
|
|
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
|
|
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
|
|
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
|
|
|
|
/** TIMG_NTIMERS_DATE_REG register
|
|
* Timer version control register
|
|
*/
|
|
#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
|
|
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409;
|
|
* Timer version control register
|
|
*/
|
|
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
|
|
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
|
|
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
|
|
#define TIMG_NTIMGS_DATE_S 0
|
|
|
|
/** TIMG_REGCLK_REG register
|
|
* Timer group clock gate register
|
|
*/
|
|
#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
|
|
/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
|
|
* enable WDT's clock
|
|
*/
|
|
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
|
|
#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S)
|
|
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U
|
|
#define TIMG_WDT_CLK_IS_ACTIVE_S 29
|
|
/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1;
|
|
* enable Timer $x's clock
|
|
*/
|
|
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
|
|
#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S)
|
|
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U
|
|
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
|
|
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
|
|
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
|
|
* Registers can not be read or written to by software.
|
|
*/
|
|
#define TIMG_CLK_EN (BIT(31))
|
|
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
|
|
#define TIMG_CLK_EN_V 0x00000001U
|
|
#define TIMG_CLK_EN_S 31
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|