kopia lustrzana https://github.com/espressif/esp-idf
326 wiersze
11 KiB
C
326 wiersze
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Timer Group register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/timer_periph.h"
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#include "soc/timer_group_struct.h"
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#include "soc/pcr_struct.h"
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#include "hal/wdt_types.h"
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#include "hal/assert.h"
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#include "esp_attr.h"
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#include "hal/misc.h"
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/* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
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#define MWDT_LL_DEFAULT_CLK_PRESCALER 24000
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/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
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#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
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/* Possible values for TIMG_WDT_STGx */
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#define TIMG_WDT_STG_SEL_OFF 0
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#define TIMG_WDT_STG_SEL_INT 1
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#define TIMG_WDT_STG_SEL_RESET_CPU 2
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#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
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#define TIMG_WDT_RESET_LENGTH_100_NS 0
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#define TIMG_WDT_RESET_LENGTH_200_NS 1
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#define TIMG_WDT_RESET_LENGTH_300_NS 2
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#define TIMG_WDT_RESET_LENGTH_400_NS 3
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#define TIMG_WDT_RESET_LENGTH_500_NS 4
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#define TIMG_WDT_RESET_LENGTH_800_NS 5
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#define TIMG_WDT_RESET_LENGTH_1600_NS 6
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#define TIMG_WDT_RESET_LENGTH_3200_NS 7
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//Type check wdt_stage_action_t
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ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == TIMG_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == TIMG_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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//Type check wdt_reset_sig_length_t
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == TIMG_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == TIMG_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == TIMG_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == TIMG_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == TIMG_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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/**
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* @brief Enable the MWDT
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
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{
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hw->wdtconfig0.wdt_en = 1;
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}
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/**
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* @brief Disable the MWDT
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*
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* @param hw Start address of the peripheral registers.
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* @note This function does not disable the flashboot mode. Therefore, given that
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* the MWDT is disabled using this function, a timeout can still occur
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* if the flashboot mode is simultaneously enabled.
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*/
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FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
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{
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hw->wdtconfig0.wdt_en = 0;
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}
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/**
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* Check if the MWDT is enabled
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*
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* @param hw Start address of the peripheral registers.
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* @return True if the MWDT is enabled, false otherwise
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*/
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FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
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{
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return (hw->wdtconfig0.wdt_en) ? true : false;
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}
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/**
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* @brief Configure a particular stage of the MWDT
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*
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* @param hw Start address of the peripheral registers.
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* @param stage Which stage to configure
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* @param timeout Number of timer ticks for the stage to timeout
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* @param behavior What action to take when the stage times out
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*/
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FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior)
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{
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switch (stage) {
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case WDT_STAGE0:
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hw->wdtconfig0.wdt_stg0 = behavior;
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hw->wdtconfig2.wdt_stg0_hold = timeout;
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break;
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case WDT_STAGE1:
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hw->wdtconfig0.wdt_stg1 = behavior;
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hw->wdtconfig3.wdt_stg1_hold = timeout;
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break;
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case WDT_STAGE2:
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hw->wdtconfig0.wdt_stg2 = behavior;
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hw->wdtconfig4.wdt_stg2_hold = timeout;
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break;
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case WDT_STAGE3:
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hw->wdtconfig0.wdt_stg3 = behavior;
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hw->wdtconfig5.wdt_stg3_hold = timeout;
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break;
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default:
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HAL_ASSERT(false && "unsupported WDT stage");
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break;
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}
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//Config registers are updated asynchronously
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hw->wdtconfig0.wdt_conf_update_en = 1;
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}
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/**
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* @brief Disable a particular stage of the MWDT
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*
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* @param hw Start address of the peripheral registers.
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* @param stage Which stage to disable
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*/
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FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
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{
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switch (stage) {
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case WDT_STAGE0:
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hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
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break;
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case WDT_STAGE1:
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hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
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break;
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case WDT_STAGE2:
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hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
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break;
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case WDT_STAGE3:
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hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
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break;
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default:
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HAL_ASSERT(false && "unsupported WDT stage");
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break;
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}
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//Config registers are updated asynchronously
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hw->wdtconfig0.wdt_conf_update_en = 1;
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}
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/**
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* @brief Set the length of the CPU reset action
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*
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* @param hw Start address of the peripheral registers.
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* @param length Length of CPU reset signal
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*/
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FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
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{
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hw->wdtconfig0.wdt_cpu_reset_length = length;
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//Config registers are updated asynchronously
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hw->wdtconfig0.wdt_conf_update_en = 1;
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}
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/**
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* @brief Set the length of the system reset action
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*
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* @param hw Start address of the peripheral registers.
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* @param length Length of system reset signal
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*/
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FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
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{
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hw->wdtconfig0.wdt_sys_reset_length = length;
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//Config registers are updated asynchronously
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hw->wdtconfig0.wdt_conf_update_en = 1;
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}
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/**
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* @brief Enable/Disable the MWDT flashboot mode.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param enable True to enable WDT flashboot mode, false to disable WDT flashboot mode.
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*
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* @note Flashboot mode is independent and can trigger a WDT timeout event if the
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* WDT's enable bit is set to 0. Flashboot mode for TG0 is automatically enabled
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* on flashboot, and should be disabled by software when flashbooting completes.
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*/
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FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
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{
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hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
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//Config registers are updated asynchronously
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hw->wdtconfig0.wdt_conf_update_en = 1;
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}
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/**
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* @brief Set the clock prescaler of the MWDT
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*
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* @param hw Start address of the peripheral registers.
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* @param prescaler Prescaler value between 1 to 65535
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*/
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FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
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{
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// In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register)
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// We take care of the "read-modify-write" procedure by ourselves.
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler);
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//Config registers are updated asynchronously
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hw->wdtconfig0.wdt_conf_update_en = 1;
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}
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/**
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* @brief Feed the MWDT
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*
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* Resets the current timer count and current stage.
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
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{
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hw->wdtfeed.wdt_feed = 1;
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}
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/**
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* @brief Enable write protection of the MWDT registers
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*
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* Locking the MWDT will prevent any of the MWDT's registers from being modified
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
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{
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hw->wdtwprotect.wdt_wkey = 0;
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}
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/**
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* @brief Disable write protection of the MWDT registers
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
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{
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hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
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}
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/**
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* @brief Clear the MWDT interrupt status.
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
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{
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hw->int_clr_timers.wdt_int_clr = 1;
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}
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/**
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* @brief Set the interrupt enable bit for the MWDT interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param enable Whether to enable the MWDT interrupt
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*/
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FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable)
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{
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hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0;
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}
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/**
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* @brief Set the clock source for the MWDT.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param clk_src Clock source
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*/
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FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_source_t clk_src)
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{
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uint8_t clk_id = 0;
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switch (clk_src) {
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case MWDT_CLK_SRC_XTAL:
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clk_id = 0;
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break;
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case MWDT_CLK_SRC_RC_FAST:
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clk_id = 1;
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break;
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case MWDT_CLK_SRC_PLL_F48M:
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clk_id = 2;
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break;
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default:
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HAL_ASSERT(false);
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break;
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}
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if (hw == &TIMERG0) {
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PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_sel = clk_id;
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} else {
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PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_sel = clk_id;
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}
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}
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/**
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* @brief Enable MWDT module clock
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*
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* @param hw Beginning address of the peripheral registers.
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* @param en true to enable, false to disable
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*/
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__attribute__((always_inline))
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static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en)
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{
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if (hw == &TIMERG0) {
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PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en;
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} else {
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PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en;
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}
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}
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#ifdef __cplusplus
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}
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#endif
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