kopia lustrzana https://github.com/espressif/esp-idf
268 wiersze
7.8 KiB
ArmAsm
268 wiersze
7.8 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include "freertos/xtensa_context.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#if CONFIG_BTDM_CTRL_HLI
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/* Interrupt stack size, for C code.
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* TODO: reduce and make configurable.
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*/
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#define L4_INTR_STACK_SIZE 4096
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/* Save area for the CPU state:
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* - 64 words for the general purpose registers
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* - 7 words for some of the special registers:
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* - WINDOWBASE, WINDOWSTART — only WINDOWSTART is truly needed
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* - SAR, LBEG, LEND, LCOUNT — since the C code might use these
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* - EPC1 — since the C code might cause window overflow exceptions
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* This is not laid out as standard exception frame structure
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* for simplicity of the save/restore code.
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*/
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#define REG_FILE_SIZE (64 * 4)
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#define SPECREG_OFFSET REG_FILE_SIZE
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#define SPECREG_SIZE (7 * 4)
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#define REG_SAVE_AREA_SIZE (SPECREG_OFFSET + SPECREG_SIZE)
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.data
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_l4_intr_stack:
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.space L4_INTR_STACK_SIZE
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_l4_save_ctx:
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.space REG_SAVE_AREA_SIZE
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.section .iram1,"ax"
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.global xt_highint4
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.type xt_highint4,@function
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.align 4
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xt_highint4:
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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/*
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Here, Timer2 is used to count a little time(50us).
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The subsequent dram0 write operation is blocked due to live lock, which will
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cause timer2 to timeout and trigger a level 5 interrupt.
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*/
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rsr.ccount a0
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addmi a0, a0, (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ*50)
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wsr a0, CCOMPARE2
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/* Enable Timer 2 interrupt */
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rsr a0, INTENABLE
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extui a0, a0, 16, 1
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bnez a0, 1f
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movi a0, 0
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xsr a0, INTENABLE /* disable all interrupts */
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/* And a0 with (1 << 16) for Timer 2 interrupt mask */
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addmi a0, a0, (1<<14)
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addmi a0, a0, (1<<14)
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addmi a0, a0, (1<<14)
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addmi a0, a0, (1<<14)
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wsr a0, INTENABLE /* Enable Timer 2 */
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1:
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#endif
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movi a0, _l4_save_ctx
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/* save 4 lower registers */
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s32i a1, a0, 4
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s32i a2, a0, 8
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s32i a3, a0, 12
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rsr a2, EXCSAVE_4 /* holds the value of a0 */
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s32i a2, a0, 0
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/* Save special registers */
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addi a0, a0, SPECREG_OFFSET
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rsr a2, WINDOWBASE
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s32i a2, a0, 0
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rsr a2, WINDOWSTART
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s32i a2, a0, 4
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rsr a2, SAR
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s32i a2, a0, 8
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rsr a2, LBEG
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s32i a2, a0, 12
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rsr a2, LEND
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s32i a2, a0, 16
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rsr a2, LCOUNT
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s32i a2, a0, 20
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rsr a2, EPC1
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s32i a2, a0, 24
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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movi a0, 0
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xsr a0, INTENABLE /* disable all interrupts */
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movi a2, ~(1<<16)
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and a0, a2, a0
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wsr a0, INTENABLE
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#endif
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/* disable exception mode, window overflow */
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movi a0, PS_INTLEVEL(5) | PS_EXCM
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wsr a0, PS
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rsync
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/* Save the remaining physical registers.
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* 4 registers are already saved, which leaves 60 registers to save.
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* (FIXME: consider the case when the CPU is configured with physical 32 registers)
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* These 60 registers are saved in 5 iterations, 12 registers at a time.
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*/
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movi a1, 5
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movi a3, _l4_save_ctx + 4 * 4
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/* This is repeated 5 times, each time the window is shifted by 12 registers.
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* We come here with a1 = downcounter, a3 = save pointer, a2 and a0 unused.
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*/
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1:
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s32i a4, a3, 0
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s32i a5, a3, 4
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s32i a6, a3, 8
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s32i a7, a3, 12
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s32i a8, a3, 16
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s32i a9, a3, 20
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s32i a10, a3, 24
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s32i a11, a3, 28
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s32i a12, a3, 32
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s32i a13, a3, 36
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s32i a14, a3, 40
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s32i a15, a3, 44
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/* We are about to rotate the window, so that a12-a15 will become the new a0-a3.
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* Copy a0-a3 to a12-15 to still have access to these values.
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* At the same time we can decrement the counter and adjust the save area pointer
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*/
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/* a0 is constant (_l4_save_ctx), no need to copy */
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addi a13, a1, -1 /* copy and decrement the downcounter */
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/* a2 is scratch so no need to copy */
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addi a15, a3, 48 /* copy and adjust the save area pointer */
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beqz a13, 2f /* have saved all registers ? */
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rotw 3 /* rotate the window and go back */
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j 1b
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/* the loop is complete */
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2:
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rotw 4 /* this brings us back to the original window */
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/* a0 still points to _l4_save_ctx */
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/* Can clear WINDOWSTART now, all registers are saved */
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rsr a2, WINDOWBASE
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/* WINDOWSTART = (1 << WINDOWBASE) */
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movi a3, 1
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ssl a2
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sll a3, a3
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wsr a3, WINDOWSTART
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_highint4_stack_switch:
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movi a0, 0
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movi sp, _l4_intr_stack + L4_INTR_STACK_SIZE - 16
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s32e a0, sp, -12 /* For GDB: set null SP */
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s32e a0, sp, -16 /* For GDB: set null PC */
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movi a0, _highint4_stack_switch /* For GDB: cosmetics, for the frame where stack switch happened */
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/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
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movi a6, PS_INTLEVEL(4) | PS_UM | PS_WOE
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wsr a6, PS
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rsync
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/* Call C handler */
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mov a6, sp
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call4 hli_c_handler
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l32e sp, sp, -12 /* switch back to the original stack */
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/* Done with C handler; re-enable exception mode, disabling window overflow */
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movi a2, PS_INTLEVEL(5) | PS_EXCM /* TOCHECK */
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wsr a2, PS
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rsync
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/* Restore the special registers.
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* WINDOWSTART will be restored near the end.
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*/
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movi a0, _l4_save_ctx + SPECREG_OFFSET
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l32i a2, a0, 8
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wsr a2, SAR
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l32i a2, a0, 12
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wsr a2, LBEG
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l32i a2, a0, 16
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wsr a2, LEND
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l32i a2, a0, 20
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wsr a2, LCOUNT
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l32i a2, a0, 24
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wsr a2, EPC1
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/* Restoring the physical registers.
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* This is the reverse to the saving process above.
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*/
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/* Rotate back to the final window, then start loading 12 registers at a time,
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* in 5 iterations.
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* Again, a1 is the downcounter and a3 is the save area pointer.
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* After each rotation, a1 and a3 are copied from a13 and a15.
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* To simplify the loop, we put the initial values into a13 and a15.
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*/
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rotw -4
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movi a15, _l4_save_ctx + 64 * 4 /* point to the end of the save area */
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movi a13, 5
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1:
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/* Copy a1 and a3 from their previous location,
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* at the same time decrementing and adjusting the save area pointer.
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*/
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addi a1, a13, -1
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addi a3, a15, -48
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/* Load 12 registers */
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l32i a4, a3, 0
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l32i a5, a3, 4
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l32i a6, a3, 8
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l32i a7, a3, 12
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l32i a8, a3, 16
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l32i a9, a3, 20
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l32i a10, a3, 24
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l32i a11, a3, 28 /* ensure PS and EPC written */
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l32i a12, a3, 32
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l32i a13, a3, 36
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l32i a14, a3, 40
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l32i a15, a3, 44
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/* Done with the loop? */
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beqz a1, 2f
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/* If no, rotate the window and repeat */
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rotw -3
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j 1b
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2:
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/* Done with the loop. Only 4 registers (a0-a3 in the original window) remain
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* to be restored. Also need to restore WINDOWSTART, since all the general
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* registers are now in place.
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*/
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movi a0, _l4_save_ctx
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l32i a2, a0, SPECREG_OFFSET + 4
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wsr a2, WINDOWSTART
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l32i a1, a0, 4
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l32i a2, a0, 8
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l32i a3, a0, 12
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rsr a0, EXCSAVE_4 /* holds the value of a0 before the interrupt handler */
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/* Return from the interrupt, restoring PS from EPS_4 */
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rfi 4
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#endif /* CONFIG_BTDM_CTRL_HLI */
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/* The linker has no reason to link in this file; all symbols it exports are already defined
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(weakly!) in the default int handler. Define a symbol here so we can use it to have the
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linker inspect this anyway. */
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.global ld_include_hli_vectors_bt
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ld_include_hli_vectors_bt:
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