kopia lustrzana https://github.com/espressif/esp-idf
369 wiersze
13 KiB
C
369 wiersze
13 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Timer Group register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdlib.h>
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#include <stdbool.h>
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#include "hal/misc.h"
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#include "hal/wdt_types.h"
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#include "soc/rtc_cntl_periph.h"
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#include "soc/efuse_reg.h"
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#include "esp_attr.h"
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#include "esp_assert.h"
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#include "esp32c5/rom/ets_sys.h"
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/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
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#define LP_WDT_WKEY_VALUE 0x50D83AA1
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/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
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#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
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/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
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#define LP_WDT_RESET_LENGTH_100_NS 0
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#define LP_WDT_RESET_LENGTH_200_NS 1
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#define LP_WDT_RESET_LENGTH_300_NS 2
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#define LP_WDT_RESET_LENGTH_400_NS 3
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#define LP_WDT_RESET_LENGTH_500_NS 4
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#define LP_WDT_RESET_LENGTH_800_NS 5
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#define LP_WDT_RESET_LENGTH_1600_NS 6
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#define LP_WDT_RESET_LENGTH_3200_NS 7
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#define LP_WDT_STG_SEL_OFF 0
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#define LP_WDT_STG_SEL_INT 1
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#define LP_WDT_STG_SEL_RESET_CPU 2
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#define LP_WDT_STG_SEL_RESET_SYSTEM 3
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#define LP_WDT_STG_SEL_RESET_RTC 4
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//Type check wdt_stage_action_t
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ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == LP_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == LP_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == LP_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == LP_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == LP_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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//Type check wdt_reset_sig_length_t
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == LP_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == LP_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == LP_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == LP_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == LP_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == LP_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == LP_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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/**
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* @brief Enable the RWDT
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->config0.wdt_en = 1;
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abort();
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}
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/**
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* @brief Disable the RWDT
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*
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* @param hw Start address of the peripheral registers.
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* @note This function does not disable the flashboot mode. Therefore, given that
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* the MWDT is disabled using this function, a timeout can still occur
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* if the flashboot mode is simultaneously enabled.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->config0.wdt_en = 0;
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abort();
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}
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/**
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* @brief Check if the RWDT is enabled
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*
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* @param hw Start address of the peripheral registers.
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* @return True if RTC WDT is enabled
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*/
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FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
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{
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// TODO: [ESP32C5] IDF-8635
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// return (hw->config0.wdt_en) ? true : false;
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abort();
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return (bool)0;
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}
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/**
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* @brief Configure a particular stage of the RWDT
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*
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* @param hw Start address of the peripheral registers.
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* @param stage Which stage to configure
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* @param timeout Number of timer ticks for the stage to timeout (see note).
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* @param behavior What action to take when the stage times out
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*
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* @note The value of of RWDT stage 0 timeout register is special, in
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* that an implicit multiplier is applied to that value to produce
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* and effective timeout tick value. The multiplier is dependent
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* on an EFuse value. Therefore, when configuring stage 0, the valid
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* values for the timeout argument are:
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* - If Efuse value is 0, any even number between [2,2*UINT32_MAX]
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* - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX]
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* - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX]
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* - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX]
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
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{
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// TODO: [ESP32C5] IDF-8635
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// switch (stage) {
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// case WDT_STAGE0:
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// hw->config0.wdt_stg0 = behavior;
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// //Account of implicty multiplier applied to stage 0 timeout tick config value
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// hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
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// break;
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// case WDT_STAGE1:
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// hw->config0.wdt_stg1 = behavior;
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// hw->config2.val = timeout_ticks;
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// break;
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// case WDT_STAGE2:
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// hw->config0.wdt_stg2 = behavior;
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// hw->config3.val = timeout_ticks;
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// break;
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// case WDT_STAGE3:
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// hw->config0.wdt_stg3 = behavior;
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// hw->config4.val = timeout_ticks;
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// break;
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// default:
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// abort();
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// }
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abort();
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}
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/**
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* @brief Disable a particular stage of the RWDT
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*
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* @param hw Start address of the peripheral registers.
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* @param stage Which stage to disable
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage)
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{
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// TODO: [ESP32C5] IDF-8635
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// switch (stage) {
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// case WDT_STAGE0:
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// hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
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// break;
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// case WDT_STAGE1:
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// hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
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// break;
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// case WDT_STAGE2:
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// hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
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// break;
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// case WDT_STAGE3:
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// hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
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// break;
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// default:
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// abort();
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// }
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abort();
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}
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/**
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* @brief Set the length of the CPU reset action
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*
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* @param hw Start address of the peripheral registers.
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* @param length Length of CPU reset signal
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->config0.wdt_cpu_reset_length = length;
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abort();
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}
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/**
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* @brief Set the length of the system reset action
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*
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* @param hw Start address of the peripheral registers.
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* @param length Length of system reset signal
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->config0.wdt_sys_reset_length = length;
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abort();
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}
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/**
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* @brief Enable/Disable the RWDT flashboot mode.
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
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*
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* @note Flashboot mode is independent and can trigger a WDT timeout event if the
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* WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled
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* on flashboot, and should be disabled by software when flashbooting completes.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
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abort();
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}
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/**
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* @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable CPU0 to be reset, false to disable.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
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abort();
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}
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/**
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* @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable CPU1 to be reset, false to disable.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
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abort();
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}
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/**
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* @brief Enable/Disable the RWDT pause during sleep functionality
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable, false to disable.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
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abort();
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}
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/**
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* @brief Enable/Disable chip reset on RWDT timeout.
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*
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* A chip reset also resets the analog portion of the chip. It will appear as a
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* POWERON reset rather than an RTC reset.
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable, false to disable.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0;
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abort();
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}
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/**
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* @brief Set width of chip reset signal
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*
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* @param hw Start address of the peripheral registers.
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* @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width)
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{
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// TODO: [ESP32C5] IDF-8635
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// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width);
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abort();
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}
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/**
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* @brief Feed the RWDT
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*
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* Resets the current timer count and current stage.
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->feed.rtc_wdt_feed = 1;
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abort();
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}
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/**
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* @brief Enable write protection of the RWDT registers
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->wprotect.val = 0;
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abort();
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}
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/**
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* @brief Disable write protection of the RWDT registers
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->wprotect.val = LP_WDT_WKEY_VALUE;
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abort();
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}
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/**
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* @brief Enable the RWDT interrupt.
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable RWDT interrupt, false to disable.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
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abort();
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}
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/**
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* @brief Check if the RWDT interrupt has been triggered
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*
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* @param hw Start address of the peripheral registers.
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* @return True if the RWDT interrupt was triggered
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*/
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FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
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{
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// TODO: [ESP32C5] IDF-8635
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// return (hw->int_st.lp_wdt_int_st) ? true : false;
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abort();
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return (bool)0;
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}
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/**
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* @brief Clear the RWDT interrupt status.
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw)
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{
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// TODO: [ESP32C5] IDF-8635
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// hw->int_clr.lp_wdt_int_clr = 1;
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abort();
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}
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#ifdef __cplusplus
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}
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#endif
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