kopia lustrzana https://github.com/espressif/esp-idf
230 wiersze
8.4 KiB
C
230 wiersze
8.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "unity.h"
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#include "test_utils.h"
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#include "esp_heap_caps.h"
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#include "driver/spi_master.h"
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#include "esp_private/spi_master_internal.h"
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#include "driver/spi_slave_hd.h"
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#include "driver/spi_slave.h"
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#include "soc/spi_pins.h"
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#include "test_spi_utils.h"
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__attribute__((unused)) static const char *TAG = "SCT";
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#if (SOC_SPI_SUPPORT_SLAVE_HD_VER2 && SOC_SPI_SCT_SUPPORTED)
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/*-----------------------------------------------------------
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* HD SCT Functional Test
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*-----------------------------------------------------------*/
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#define TEST_HD_TIMES 4
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//Master write, slave read, wrt slave reg
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#define TEST_HD_BUF_0_ID 12
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#define TEST_HD_BUF_0_VAL 0x99
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//Master read, slave write, wrt slave reg
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#define TEST_HD_BUF_1_ID 13
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#define TEST_HD_BUF_1_VAL 0xAA
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#define TEST_HD_DATA_LEN 64
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#define TEST_HD_DATA_LEN_PER_SEG 32
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static void hd_master(void)
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{
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spi_device_handle_t handle;
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spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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buscfg.max_transfer_sz = 4092 * 10;
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spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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devcfg.command_bits = 8;
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devcfg.address_bits = 8;
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devcfg.dummy_bits = 8;
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devcfg.clock_speed_hz = 10 * 1000;
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devcfg.input_delay_ns = 0;
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devcfg.flags = SPI_DEVICE_HALFDUPLEX;
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TEST_ESP_OK(spi_bus_initialize(SPI2_HOST, &buscfg, SPI_DMA_CH_AUTO));
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TEST_ESP_OK(spi_bus_add_device(SPI2_HOST, &devcfg, &handle));
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unity_send_signal("Master ready");
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//Test data preparation
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uint32_t master_tx_val = TEST_HD_BUF_0_VAL;
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uint8_t *master_tx_buf = heap_caps_calloc(1, TEST_HD_DATA_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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uint8_t *master_rx_buf = heap_caps_calloc(1, TEST_HD_DATA_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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uint32_t master_rx_val = 0;
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uint8_t *slave_tx_buf = heap_caps_calloc(1, TEST_HD_DATA_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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test_fill_random_to_buffers_dualboard(199, master_tx_buf, slave_tx_buf, TEST_HD_DATA_LEN);
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spi_multi_transaction_t *ret_seg_trans = NULL;
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//---------------------Master TX---------------------------//
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spi_multi_transaction_t tx_seg_trans[TEST_HD_TIMES] = {
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{
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.base = {
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.cmd = 0x1,
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.addr = TEST_HD_BUF_0_ID,
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.length = 4 * 8,
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.tx_buffer = (uint8_t *) &master_tx_val,
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},
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},
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//TEST_HD_DATA_LEN of TX data, splitted into 2 segments. `TEST_HD_DATA_LEN_PER_SEG` per segment
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{
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.base = {
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.cmd = 0x3,
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.length = TEST_HD_DATA_LEN_PER_SEG * 8,
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.tx_buffer = master_tx_buf,
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},
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.dummy_bits = 8,
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.seg_trans_flags = SPI_MULTI_TRANS_DUMMY_LEN_UPDATED,
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},
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{
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.base = {
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.cmd = 0x3,
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.length = TEST_HD_DATA_LEN_PER_SEG * 8,
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.tx_buffer = master_tx_buf + TEST_HD_DATA_LEN_PER_SEG,
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},
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.dummy_bits = 8,
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.seg_trans_flags = SPI_MULTI_TRANS_DUMMY_LEN_UPDATED,
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},
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{
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.base = {
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.cmd = 0x7,
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}
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},
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};
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TEST_ESP_OK(spi_bus_multi_trans_mode_enable(handle, true));
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unity_wait_for_signal("Slave ready");
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TEST_ESP_OK(spi_device_queue_multi_trans(handle, tx_seg_trans, TEST_HD_TIMES, portMAX_DELAY));
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TEST_ESP_OK(spi_device_get_multi_trans_result(handle, &ret_seg_trans, portMAX_DELAY));
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TEST_ASSERT(ret_seg_trans == tx_seg_trans);
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ESP_LOG_BUFFER_HEX("Master tx", master_tx_buf, TEST_HD_DATA_LEN);
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TEST_ESP_OK(spi_bus_multi_trans_mode_enable(handle, false));
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//---------------------Master RX---------------------------//
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spi_multi_transaction_t rx_seg_trans[TEST_HD_TIMES] = {
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{
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.base = {
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.cmd = 0x2,
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.addr = TEST_HD_BUF_1_ID,
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.rxlength = 4 * 8,
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.rx_buffer = (uint8_t *) &master_rx_val,
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},
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},
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// TEST_HD_DATA_LEN of TX data, splitted into 2 segments. `TEST_HD_DATA_LEN_PER_SEG` per segment
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{
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.base = {
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.cmd = 0x4,
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.rxlength = TEST_HD_DATA_LEN_PER_SEG * 8,
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.rx_buffer = master_rx_buf,
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},
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.dummy_bits = 8,
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.seg_trans_flags = SPI_MULTI_TRANS_DUMMY_LEN_UPDATED,
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},
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{
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.base = {
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.cmd = 0x4,
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.rxlength = TEST_HD_DATA_LEN_PER_SEG * 8,
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.rx_buffer = master_rx_buf + TEST_HD_DATA_LEN_PER_SEG,
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},
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.dummy_bits = 8,
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.seg_trans_flags = SPI_MULTI_TRANS_DUMMY_LEN_UPDATED,
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},
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{
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.base = {
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.cmd = 0x8,
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}
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},
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};
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TEST_ESP_OK(spi_bus_multi_trans_mode_enable(handle, true));
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unity_wait_for_signal("Slave ready");
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TEST_ESP_OK(spi_device_queue_multi_trans(handle, rx_seg_trans, TEST_HD_TIMES, portMAX_DELAY));
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TEST_ESP_OK(spi_device_get_multi_trans_result(handle, &ret_seg_trans, portMAX_DELAY));
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TEST_ASSERT(ret_seg_trans == rx_seg_trans);
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ESP_LOGI("Master", "Slave Reg[%d] value is: 0x%" PRIx32, TEST_HD_BUF_1_ID, master_rx_val);
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TEST_ASSERT(master_rx_val == TEST_HD_BUF_1_VAL);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_tx_buf, master_rx_buf, TEST_HD_DATA_LEN);
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ESP_LOG_BUFFER_HEX("Master rx", master_rx_buf, TEST_HD_DATA_LEN);
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//Memory Recycle
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free(master_tx_buf);
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free(master_rx_buf);
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free(slave_tx_buf);
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TEST_ESP_OK(spi_bus_remove_device(handle));
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TEST_ESP_OK(spi_bus_free(SPI2_HOST));
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}
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static void hd_slave(void)
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{
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spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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spi_slave_hd_slot_config_t slave_hd_cfg = SPI_SLOT_TEST_DEFAULT_CONFIG();
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slave_hd_cfg.dma_chan = SPI_DMA_CH_AUTO,
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TEST_ESP_OK(spi_slave_hd_init(SPI2_HOST, &buscfg, &slave_hd_cfg));
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spi_slave_hd_data_t *ret_trans = NULL;
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//Test data preparation
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uint32_t slave_tx_val = TEST_HD_BUF_1_VAL;
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uint8_t *slave_tx_buf = heap_caps_calloc(1, TEST_HD_DATA_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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uint8_t *slave_rx_buf = heap_caps_calloc(1, TEST_HD_DATA_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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uint32_t slave_rx_val = 0;
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uint8_t *master_tx_buf = heap_caps_calloc(1, TEST_HD_DATA_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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test_fill_random_to_buffers_dualboard(199, master_tx_buf, slave_tx_buf, TEST_HD_DATA_LEN);
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unity_wait_for_signal("Master ready");
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//---------------------Slave RX---------------------------//
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spi_slave_hd_data_t slave_rx_trans = {
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.data = slave_rx_buf,
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.len = TEST_HD_DATA_LEN,
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};
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TEST_ESP_OK(spi_slave_hd_queue_trans(SPI2_HOST, SPI_SLAVE_CHAN_RX, &slave_rx_trans, portMAX_DELAY));
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unity_send_signal("Slave ready");
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TEST_ESP_OK(spi_slave_hd_get_trans_res(SPI2_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
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TEST_ASSERT(ret_trans == &slave_rx_trans);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(master_tx_buf, slave_rx_buf, TEST_HD_DATA_LEN);
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ESP_LOG_BUFFER_HEX("Slave rx", slave_rx_buf, TEST_HD_DATA_LEN);
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spi_slave_hd_read_buffer(SPI2_HOST, TEST_HD_BUF_0_ID, (uint8_t *)&slave_rx_val, 4);
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ESP_LOGI("Slave", "Slave Reg[%d] value is: 0x%" PRIx32, TEST_HD_BUF_0_ID, slave_rx_val);
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TEST_ASSERT(slave_rx_val == TEST_HD_BUF_0_VAL);
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//---------------------Slave TX---------------------------//
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spi_slave_hd_write_buffer(SPI2_HOST, TEST_HD_BUF_1_ID, (uint8_t *)&slave_tx_val, 4);
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spi_slave_hd_data_t slave_tx_trans = {
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.data = slave_tx_buf,
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.len = TEST_HD_DATA_LEN,
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};
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TEST_ESP_OK(spi_slave_hd_queue_trans(SPI2_HOST, SPI_SLAVE_CHAN_TX, &slave_tx_trans, portMAX_DELAY));
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unity_send_signal("Slave ready");
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TEST_ESP_OK(spi_slave_hd_get_trans_res(SPI2_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY));
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TEST_ASSERT(ret_trans == &slave_tx_trans);
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ESP_LOG_BUFFER_HEX("Slave tx", slave_tx_buf, TEST_HD_DATA_LEN);
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//Memory Recycle
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free(slave_tx_buf);
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free(slave_rx_buf);
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free(master_tx_buf);
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TEST_ESP_OK(spi_slave_hd_deinit(SPI2_HOST));
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}
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TEST_CASE_MULTIPLE_DEVICES("SPI_Master_SCT_HD_Functional", "[spi_ms]", hd_master, hd_slave);
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#endif //#if (SOC_SPI_SUPPORT_SLAVE_HD_VER2 && SOC_SPI_SCT_SUPPORTED)
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