kopia lustrzana https://github.com/espressif/esp-idf
476 wiersze
18 KiB
C
476 wiersze
18 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "soc/assist_debug_reg.h"
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#include "soc/interrupt_reg.h"
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#include "esp_attr.h"
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#include "riscv/csr.h"
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#include "riscv/interrupt.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*performance counter*/
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#define CSR_PCER_MACHINE 0x7e0
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#define CSR_PCMR_MACHINE 0x7e1
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#define CSR_PCCR_MACHINE 0x7e2
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#if SOC_CPU_HAS_FPU
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/* FPU bits in mstatus start at bit 13 */
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#define CSR_MSTATUS_FPU_SHIFT 13
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/* FPU registers are clean if bits are 0b10 */
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#define CSR_MSTATUS_FPU_CLEAN_STATE 2
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/* FPU status in mstatus are represented with two bits */
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#define CSR_MSTATUS_FPU_MASK 3
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/* FPU is enabled when writing 1 to FPU bits */
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#define CSR_MSTATUS_FPU_ENA BIT(13)
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/* Set FPU registers state to clean (after being dirty) */
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#define CSR_MSTATUS_FPU_CLEAR BIT(13)
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#endif /* SOC_CPU_HAS_FPU */
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/* SW defined level which the interrupt module will mask interrupt with priority less than threshold during critical sections
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and spinlocks */
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#define RVHAL_EXCM_LEVEL 4
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/* SW defined interrupt threshold level to allow all interrupts */
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#if SOC_INT_CLIC_SUPPORTED
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/* set global CLIC masking level. When CLIC is supported, all interrupt priority levels less than or equal to the threshold level are masked. */
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#define RVHAL_INTR_ENABLE_THRESH 0
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#else
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#define RVHAL_INTR_ENABLE_THRESH 1
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#endif /* SOC_INT_CLIC_SUPPORTED */
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/* On CLIC, the interrupt threshold is stored in the upper (NLBITS) of the mintthresh register, with the other (8 - NLBITS)
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* defaulted to 1. We form the interrupt level bits here to avoid doing this at run time */
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#if SOC_INT_CLIC_SUPPORTED
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/* Helper macro to translate absolute interrupt level to CLIC interrupt threshold bits in the mintthresh reg */
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#define CLIC_INT_THRESH(intlevel) (((((intlevel) << (8 - NLBITS))) | 0x1f) << CLIC_CPU_INT_THRESH_S)
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/* Helper macro to set interrupt level RVHAL_EXCM_LEVEL. Used during critical sections */
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#define RVHAL_EXCM_LEVEL_CLIC (CLIC_INT_THRESH(RVHAL_EXCM_LEVEL - 1))
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/* Helper macro to enable interrupts. */
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#define RVHAL_INTR_ENABLE_THRESH_CLIC (CLIC_INT_THRESH(RVHAL_INTR_ENABLE_THRESH))
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#endif /* SOC_INT_CLIC_SUPPORTED */
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/* --------------------------------------------------- CPU Control -----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_wait_for_intr(void)
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{
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asm volatile ("wfi\n");
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}
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/* -------------------------------------------------- CPU Registers ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR __attribute__((pure)) uint32_t rv_utils_get_core_id(void)
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{
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#if SOC_CPU_CORES_NUM == 1
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return 0; // No need to check core ID on single core hardware
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#else
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uint32_t cpuid;
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cpuid = RV_READ_CSR(mhartid);
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return cpuid;
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#endif
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}
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FORCE_INLINE_ATTR void *rv_utils_get_sp(void)
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{
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void *sp;
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asm volatile ("mv %0, sp;" : "=r" (sp));
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return sp;
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}
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FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_get_cycle_count(void)
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{
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#if SOC_INT_CLIC_SUPPORTED
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//TODO: IDF-7848
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return RV_READ_CSR(mcycle);
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#else
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return RV_READ_CSR(CSR_PCCR_MACHINE);
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#endif
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}
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FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_set_cycle_count(uint32_t ccount)
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{
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#if SOC_INT_CLIC_SUPPORTED
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//TODO: IDF-7848
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RV_WRITE_CSR(mcycle, ccount);
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#else
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RV_WRITE_CSR(CSR_PCCR_MACHINE, ccount);
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#endif
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}
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/* ------------------------------------------------- CPU Interrupts ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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// ---------------- Interrupt Descriptors ------------------
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// --------------- Interrupt Configuration -----------------
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#if SOC_INT_CLIC_SUPPORTED
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FORCE_INLINE_ATTR void rv_utils_set_mtvt(uint32_t mtvt_val)
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{
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#define MTVT 0x307
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RV_WRITE_CSR(MTVT, mtvt_val);
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}
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#endif
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FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val)
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{
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#if SOC_INT_CLIC_SUPPORTED
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mtvec_val |= 3; // Set MODE field to 3 to treat MTVT + 4*interrupt_id as the service entry address for HW vectored interrupts
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#else
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mtvec_val |= 1; // Set MODE field to treat MTVEC as a vector base address
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#endif
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RV_WRITE_CSR(mtvec, mtvec_val);
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}
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// TODO: [ESP32C5] IDF-8655 need refactor for C5 MP
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#if SOC_INT_CLIC_SUPPORTED && !CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
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FORCE_INLINE_ATTR __attribute__((pure)) uint32_t rv_utils_get_interrupt_level(void)
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{
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#if CONFIG_IDF_TARGET_ESP32P4
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// As per CLIC specs, mintstatus CSR should be at 0xFB1, however esp32p4 implements it at 0x346
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#define MINTSTATUS 0x346
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#elif CONFIG_IDF_TARGET_ESP32C5
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// TODO: [ESP32C5] IDF-8654, IDF-8655 (inherit from P4) Check the correctness
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#define MINTSTATUS 0x346
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#elif CONFIG_IDF_TARGET_ESP32C61
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// TODO: [ESP32C61] IDF-9261, IDF-9262 (inherit from c6) Check
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#define MINTSTATUS 0xFB1
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#define MINTTHRESH 0x347
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#else
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#error "rv_utils_get_mintstatus() is not implemented. Check for correct mintstatus register address."
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#endif /* CONFIG_IDF_TARGET_ESP32P4 */
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uint32_t mintstatus = RV_READ_CSR(MINTSTATUS);
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return ((mintstatus >> 24) & 0xFF); // Return the mintstatus[31:24] bits to get the mil field
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}
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#endif /* SOC_INT_CLIC_SUPPORTED */
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// ------------------ Interrupt Control --------------------
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FORCE_INLINE_ATTR void rv_utils_intr_enable(uint32_t intr_mask)
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{
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// Disable all interrupts to make updating of the interrupt mask atomic.
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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esprv_int_enable(intr_mask);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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}
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FORCE_INLINE_ATTR void rv_utils_intr_disable(uint32_t intr_mask)
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{
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// Disable all interrupts to make updating of the interrupt mask atomic.
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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esprv_int_disable(intr_mask);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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}
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#if SOC_INT_CLIC_SUPPORTED
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FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_restore_intlevel(uint32_t restoreval)
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{
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// TODO: [ESP32C5] IDF-8655 need refactor for C5 MP
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#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
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#define MINTTHRESH 0x347
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RV_WRITE_CSR(MINTTHRESH, restoreval);
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#elif CONFIG_IDF_TARGET_ESP32C61
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// TODO: [ESP32C61] IDF-9261, changed in verify code, pls check
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// RV_WRITE_CSR(MINTTHRESH, restoreval);
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#else
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REG_SET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH, ((restoreval << (8 - NLBITS))) | 0x1f);
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#endif // !CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
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}
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FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_set_intlevel(uint32_t intlevel)
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{
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uint32_t old_thresh;
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// TODO: [ESP32C5] IDF-8655 need refactor for C5 MP
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#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
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old_thresh = RV_READ_CSR(MINTTHRESH);
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RV_WRITE_CSR(MINTTHRESH, ((intlevel << (8 - NLBITS)) | 0x1f));
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#else
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// TODO: [ESP32C61] IDF-9261 pls check
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uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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old_thresh = REG_GET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH);
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old_thresh = (old_thresh >> (8 - NLBITS));
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/* Upper bits should already be 0, but let's be safe and keep NLBITS */
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old_thresh &= BIT(NLBITS) - 1;
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REG_SET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH, ((intlevel << (8 - NLBITS))) | 0x1f);
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/**
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* After writing the threshold register, the new threshold is not directly taken into account by the CPU.
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* By executing ~8 nop instructions, or by performing a memory load right now, the previous memory write
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* operations is forced, making the new threshold active. It is then safe to re-enable MIE bit in mstatus.
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*/
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REG_READ(CLIC_INT_THRESH_REG);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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#endif
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return old_thresh;
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}
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/* Direct register write version of rv_utils_restore_intlevel(). Used to speed up critical sections. */
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FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_restore_intlevel_regval(uint32_t restoreval)
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{
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/* This function expects restoreval to be in the format needed to restore the interrupt level with
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* a single write to the mintthresh register without further manipulations needed.
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* This is done to quicken up exit for critical sections */
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REG_WRITE(CLIC_INT_THRESH_REG, restoreval);
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}
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/* Direct register write version of rv_utils_set_intlevel(). Used to speed up critical sections. */
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FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_set_intlevel_regval(uint32_t intlevel)
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{
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uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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uint32_t old_thresh = REG_READ(CLIC_INT_THRESH_REG);
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/* This function expects the interrupt level to be available in the format needed for mintthresh reg.
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* Providing an absolute interrupt level will result in incorrect behavior.
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* See CLIC_INT_THRESH() macro for details of how the interrupt level must be provided. */
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REG_WRITE(CLIC_INT_THRESH_REG, intlevel);
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/**
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* After writing the threshold register, the new threshold is not directly taken into account by the CPU.
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* By executing ~8 nop instructions, or by performing a memory load right now, the previous memory write
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* operations is forced, making the new threshold active. It is then safe to re-enable MIE bit in mstatus.
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*/
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REG_READ(CLIC_INT_THRESH_REG);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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/* We return the mintthresh register value and NOT the absolute interrupt threshold level.
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* This is done to avoid extra bit manipulations during critical sections. */
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return old_thresh;
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}
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FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_mask_int_level_lower_than(uint32_t intlevel)
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{
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/* CLIC's set interrupt level is inclusive, i.e. it does mask the set level */
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return rv_utils_set_intlevel(intlevel - 1);
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}
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#endif /* SOC_INT_CLIC_SUPPORTED */
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FORCE_INLINE_ATTR uint32_t rv_utils_intr_get_enabled_mask(void)
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{
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#if SOC_INT_CLIC_SUPPORTED
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unsigned intr_ena_mask = 0;
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unsigned intr_num;
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for (intr_num = 0; intr_num < 32; intr_num++) {
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if (REG_GET_BIT(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_IE))
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intr_ena_mask |= BIT(intr_num);
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}
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return intr_ena_mask;
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#else
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return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
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#endif
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}
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FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(unsigned int intr_num)
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{
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#if SOC_INT_CLIC_SUPPORTED
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REG_SET_BIT(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET) , CLIC_INT_IP);
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#else
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REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num);
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#endif
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}
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FORCE_INLINE_ATTR void rv_utils_intr_global_enable(void)
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{
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RV_SET_CSR(mstatus, MSTATUS_MIE);
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}
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FORCE_INLINE_ATTR void rv_utils_intr_global_disable(void)
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{
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RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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}
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#if SOC_CPU_HAS_FPU
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/* ------------------------------------------------- FPU Related ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR bool rv_utils_enable_fpu(void)
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{
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/* Set mstatus[14:13] to 0b01 to start the floating-point unit initialization */
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RV_SET_CSR(mstatus, CSR_MSTATUS_FPU_ENA);
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/* On the ESP32-P4, the FPU can be used directly after setting `mstatus` bit 13.
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* Since the interrupt handler expects the FPU states to be either 0b10 or 0b11,
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* let's write the FPU CSR and clear the dirty bit afterwards. */
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RV_WRITE_CSR(fcsr, 1);
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RV_CLEAR_CSR(mstatus, CSR_MSTATUS_FPU_CLEAR);
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const uint32_t mstatus = RV_READ_CSR(mstatus);
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/* Make sure the FPU state is 0b10 (clean registers) */
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return ((mstatus >> CSR_MSTATUS_FPU_SHIFT) & CSR_MSTATUS_FPU_MASK) == CSR_MSTATUS_FPU_CLEAN_STATE;
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}
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FORCE_INLINE_ATTR void rv_utils_disable_fpu(void)
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{
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/* Clear mstatus[14:13] bits to disable the floating-point unit */
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RV_CLEAR_CSR(mstatus, CSR_MSTATUS_FPU_MASK << CSR_MSTATUS_FPU_SHIFT);
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}
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#endif /* SOC_CPU_HAS_FPU */
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/* -------------------------------------------------- Memory Ports -----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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/* ---------------------------------------------------- Debugging ------------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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// --------------- Breakpoints/Watchpoints -----------------
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FORCE_INLINE_ATTR void rv_utils_set_breakpoint(int bp_num, uint32_t bp_addr)
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{
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/* The code bellow sets breakpoint which will trigger `Breakpoint` exception
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* instead transfering control to debugger. */
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RV_WRITE_CSR(tselect, bp_num);
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RV_WRITE_CSR(tcontrol, TCONTROL_MPTE | TCONTROL_MTE);
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RV_WRITE_CSR(tdata1, TDATA1_USER | TDATA1_MACHINE | TDATA1_EXECUTE);
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RV_WRITE_CSR(tdata2, bp_addr);
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}
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FORCE_INLINE_ATTR void rv_utils_set_watchpoint(int wp_num,
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uint32_t wp_addr,
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size_t size,
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bool on_read,
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bool on_write)
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{
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RV_WRITE_CSR(tselect, wp_num);
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RV_WRITE_CSR(tcontrol, TCONTROL_MPTE | TCONTROL_MTE);
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RV_WRITE_CSR(tdata1, TDATA1_USER |
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TDATA1_MACHINE |
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((size == 1) ? TDATA1_MATCH_EXACT : TDATA1_MATCH_NAPOT) |
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(on_read ? TDATA1_LOAD : 0) |
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(on_write ? TDATA1_STORE : 0));
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/* From RISC-V Debug Specification:
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* tdata1(mcontrol) match = 0 : Exact byte match
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*
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* tdata1(mcontrol) match = 1 : NAPOT (Naturally Aligned Power-Of-Two):
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* Matches when the top M bits of any compare value match the top M bits of tdata2.
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* M is XLEN − 1 minus the index of the least-significant bit containing 0 in tdata2.
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* Note: Expecting that size is number power of 2 (numbers should be in the range of 1 ~ 31)
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*
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* Examples for understanding how to calculate match pattern to tdata2:
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*
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* nnnn...nnnnn 1-byte Exact byte match
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* nnnn...nnnn0 2-byte NAPOT range
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* nnnn...nnn01 4-byte NAPOT range
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* nnnn...nn011 8-byte NAPOT range
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* nnnn...n0111 16-byte NAPOT range
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* nnnn...01111 32-byte NAPOT range
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* ...
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* n011...11111 2^31 byte NAPOT range
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* * where n are bits from original address
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*/
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uint32_t match_pattern = (wp_addr & ~(size-1)) | ((size-1) >> 1);
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RV_WRITE_CSR(tdata2, match_pattern);
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}
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FORCE_INLINE_ATTR void rv_utils_clear_breakpoint(int bp_num)
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{
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RV_WRITE_CSR(tselect, bp_num);
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/* tdata1 is a WARL(write any read legal) register
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* We can just write 0 to it
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*/
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RV_WRITE_CSR(tdata1, 0);
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}
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FORCE_INLINE_ATTR void rv_utils_clear_watchpoint(int wp_num)
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{
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/* riscv have the same registers for breakpoints and watchpoints */
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rv_utils_clear_breakpoint(wp_num);
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}
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FORCE_INLINE_ATTR bool rv_utils_is_trigger_fired(int id)
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{
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RV_WRITE_CSR(tselect, id);
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return (RV_READ_CSR(tdata1) >> TDATA1_HIT_S) & 1;
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}
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// ---------------------- Debugger -------------------------
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FORCE_INLINE_ATTR bool rv_utils_dbgr_is_attached(void)
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{
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return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE);
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}
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FORCE_INLINE_ATTR void rv_utils_dbgr_break(void)
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{
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asm volatile("ebreak\n");
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}
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/* ------------------------------------------------------ Misc ---------------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR bool rv_utils_compare_and_set(volatile uint32_t *addr, uint32_t compare_value, uint32_t new_value)
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{
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#if __riscv_atomic
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uint32_t old_value = 0;
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int error = 0;
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/* Based on sample code for CAS from RISCV specs v2.2, atomic instructions */
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__asm__ __volatile__(
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"cas: lr.w %0, 0(%2) \n" // load 4 bytes from addr (%2) into old_value (%0)
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" bne %0, %3, fail \n" // fail if old_value if not equal to compare_value (%3)
|
||
" sc.w %1, %4, 0(%2) \n" // store new_value (%4) into addr,
|
||
" bnez %1, cas \n" // if we failed to store the new value then retry the operation
|
||
"fail: \n"
|
||
: "+r" (old_value), "+r" (error) // output parameters
|
||
: "r" (addr), "r" (compare_value), "r" (new_value) // input parameters
|
||
);
|
||
#else
|
||
// For a single core RV target has no atomic CAS instruction, we can achieve atomicity by disabling interrupts
|
||
unsigned old_mstatus;
|
||
old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
|
||
// Compare and set
|
||
uint32_t old_value;
|
||
old_value = *addr;
|
||
if (old_value == compare_value) {
|
||
*addr = new_value;
|
||
}
|
||
// Restore interrupts
|
||
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
|
||
|
||
#endif //__riscv_atomic
|
||
return (old_value == compare_value);
|
||
}
|
||
|
||
#if SOC_BRANCH_PREDICTOR_SUPPORTED
|
||
FORCE_INLINE_ATTR void rv_utils_en_branch_predictor(void)
|
||
{
|
||
#define MHCR 0x7c1
|
||
#define MHCR_RS (1<<4) /* R/W, address return stack set bit */
|
||
#define MHCR_BFE (1<<5) /* R/W, allow predictive jump set bit */
|
||
#define MHCR_BTB (1<<12) /* R/W, branch target prediction enable bit */
|
||
RV_SET_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB);
|
||
}
|
||
#endif
|
||
|
||
#ifdef __cplusplus
|
||
}
|
||
#endif
|