kopia lustrzana https://github.com/espressif/esp-idf
244 wiersze
8.8 KiB
C
244 wiersze
8.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include <string.h>
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#include <inttypes.h>
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#include <sys/lock.h>
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#include <sys/param.h>
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#include "esp_attr.h"
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#include "esp_check.h"
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#include "esp_ipc_isr.h"
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#include "esp_sleep.h"
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#include "esp_log.h"
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#include "esp_crc.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "esp_heap_caps.h"
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#include "soc/rtc_periph.h"
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#include "soc/soc_caps.h"
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#include "esp_private/sleep_cpu.h"
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#include "esp_private/sleep_event.h"
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#include "sdkconfig.h"
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#include "hal/rtc_hal.h"
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#include "esp32s3/rom/cache.h"
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static __attribute__((unused)) const char *TAG = "sleep";
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typedef struct {
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uint32_t start;
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uint32_t end;
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} cpu_domain_dev_regs_region_t;
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typedef struct {
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cpu_domain_dev_regs_region_t *region;
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int region_num;
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uint32_t *regs_frame;
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} cpu_domain_dev_sleep_frame_t;
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/**
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* Internal structure which holds all requested light sleep cpu retention parameters
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*/
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typedef struct {
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rtc_cntl_sleep_retent_t retent;
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} sleep_cpu_retention_t;
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static DRAM_ATTR __attribute__((unused)) sleep_cpu_retention_t s_cpu_retention;
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#if CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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static rtc_cntl_sleep_cache_tag_retent_t *s_tag_mem = &s_cpu_retention.retent.tagmem;
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static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t code_seg_size, uint32_t data_seg_vaddr, uint32_t data_seg_size)
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{
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uint32_t sets; /* i/d-cache total set counts */
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uint32_t index; /* virtual address mapping i/d-cache row offset */
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uint32_t waysgrp;
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uint32_t icache_tagmem_blk_gs, dcache_tagmem_blk_gs;
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struct cache_mode imode = { .icache = 1 };
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struct cache_mode dmode = { .icache = 0 };
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/* calculate/prepare i-cache tag memory retention parameters */
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Cache_Get_Mode(&imode);
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sets = imode.cache_size / imode.cache_ways / imode.cache_line_size;
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index = (code_seg_vaddr / imode.cache_line_size) % sets;
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waysgrp = imode.cache_ways >> 2;
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code_seg_size = ALIGNUP(imode.cache_line_size, code_seg_size);
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s_tag_mem->icache.start_point = index;
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s_tag_mem->icache.size = (sets * waysgrp) & 0xff;
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s_tag_mem->icache.vld_size = s_tag_mem->icache.size;
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if (code_seg_size < imode.cache_size / imode.cache_ways) {
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s_tag_mem->icache.vld_size = (code_seg_size / imode.cache_line_size) * waysgrp;
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}
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s_tag_mem->icache.enable = (code_seg_size != 0) ? 1 : 0;
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icache_tagmem_blk_gs = s_tag_mem->icache.vld_size ? s_tag_mem->icache.vld_size : sets * waysgrp;
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icache_tagmem_blk_gs = ALIGNUP(4, icache_tagmem_blk_gs);
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ESP_LOGD(TAG, "I-cache size:%"PRIu32" KiB, line size:%d B, ways:%d, sets:%"PRIu32", index:%"PRIu32", tag block groups:%"PRIu32"", (imode.cache_size>>10),
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imode.cache_line_size, imode.cache_ways, sets, index, icache_tagmem_blk_gs);
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/* calculate/prepare d-cache tag memory retention parameters */
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Cache_Get_Mode(&dmode);
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sets = dmode.cache_size / dmode.cache_ways / dmode.cache_line_size;
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index = (data_seg_vaddr / dmode.cache_line_size) % sets;
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waysgrp = dmode.cache_ways >> 2;
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data_seg_size = ALIGNUP(dmode.cache_line_size, data_seg_size);
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s_tag_mem->dcache.start_point = index;
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s_tag_mem->dcache.size = (sets * waysgrp) & 0x1ff;
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s_tag_mem->dcache.vld_size = s_tag_mem->dcache.size;
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#ifndef CONFIG_ESP32S3_DATA_CACHE_16KB
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if (data_seg_size < dmode.cache_size / dmode.cache_ways) {
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s_tag_mem->dcache.vld_size = (data_seg_size / dmode.cache_line_size) * waysgrp;
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}
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s_tag_mem->dcache.enable = (data_seg_size != 0) ? 1 : 0;
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#else
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s_tag_mem->dcache.enable = 1;
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#endif
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dcache_tagmem_blk_gs = s_tag_mem->dcache.vld_size ? s_tag_mem->dcache.vld_size : sets * waysgrp;
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dcache_tagmem_blk_gs = ALIGNUP(4, dcache_tagmem_blk_gs);
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ESP_LOGD(TAG, "D-cache size:%"PRIu32" KiB, line size:%d B, ways:%d, sets:%"PRIu32", index:%"PRIu32", tag block groups:%"PRIu32"", (dmode.cache_size>>10),
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dmode.cache_line_size, dmode.cache_ways, sets, index, dcache_tagmem_blk_gs);
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/* For I or D cache tagmem retention, backup and restore are performed through
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* RTC DMA (its bus width is 128 bits), For I/D Cache tagmem blocks (i-cache
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* tagmem blocks = 92 bits, d-cache tagmem blocks = 88 bits), RTC DMA automatically
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* aligns its bit width to 96 bits, therefore, 3 times RTC DMA can transfer 4
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* i/d-cache tagmem blocks (128 bits * 3 = 96 bits * 4) */
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return (((icache_tagmem_blk_gs + dcache_tagmem_blk_gs) << 2) * 3);
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}
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#endif // CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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static esp_err_t esp_sleep_tagmem_pd_low_init(void)
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{
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#if CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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if (s_tag_mem->link_addr == NULL) {
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extern char _stext[], _etext[];
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uint32_t code_start = (uint32_t)_stext;
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uint32_t code_size = (uint32_t)(_etext - _stext);
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#if !(CONFIG_SPIRAM && CONFIG_SOC_PM_SUPPORT_TAGMEM_PD)
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extern char _rodata_start[], _rodata_reserved_end[];
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uint32_t data_start = (uint32_t)_rodata_start;
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uint32_t data_size = (uint32_t)(_rodata_reserved_end - _rodata_start);
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#else
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uint32_t data_start = SOC_DROM_LOW;
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uint32_t data_size = SOC_EXTRAM_DATA_SIZE;
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#endif
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ESP_LOGI(TAG, "Code start at 0x%08"PRIx32", total %"PRIu32", data start at 0x%08"PRIx32", total %"PRIu32" Bytes",
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code_start, code_size, data_start, data_size);
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uint32_t tagmem_sz = cache_tagmem_retention_setup(code_start, code_size, data_start, data_size);
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void *buf = heap_caps_aligned_calloc(SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN, 1,
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tagmem_sz + RTC_HAL_DMA_LINK_NODE_SIZE,
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MALLOC_CAP_RETENTION);
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if (buf) {
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s_tag_mem->link_addr = rtc_cntl_hal_dma_link_init(buf,
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buf + RTC_HAL_DMA_LINK_NODE_SIZE, tagmem_sz, NULL);
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} else {
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s_tag_mem->icache.enable = 0;
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s_tag_mem->dcache.enable = 0;
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s_tag_mem->link_addr = NULL;
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return ESP_ERR_NO_MEM;
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}
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}
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#else // CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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s_tag_mem->icache.enable = 0;
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s_tag_mem->dcache.enable = 0;
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s_tag_mem->link_addr = NULL;
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#endif // CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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return ESP_OK;
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}
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static esp_err_t esp_sleep_tagmem_pd_low_deinit(void)
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{
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if (s_tag_mem->link_addr) {
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heap_caps_free(s_tag_mem->link_addr);
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s_tag_mem->icache.enable = 0;
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s_tag_mem->dcache.enable = 0;
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s_tag_mem->link_addr = NULL;
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}
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return ESP_OK;
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}
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esp_err_t esp_sleep_cpu_pd_low_init(void)
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{
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if (s_cpu_retention.retent.cpu_pd_mem == NULL) {
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void *buf = heap_caps_aligned_calloc(SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN, 1,
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SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE,
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MALLOC_CAP_RETENTION);
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if (buf) {
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s_cpu_retention.retent.cpu_pd_mem = rtc_cntl_hal_dma_link_init(buf,
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buf + RTC_HAL_DMA_LINK_NODE_SIZE, SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE, NULL);
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} else {
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return ESP_ERR_NO_MEM;
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}
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}
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if (esp_sleep_tagmem_pd_low_init() != ESP_OK) {
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#ifdef CONFIG_ESP32S3_DATA_CACHE_16KB
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esp_sleep_cpu_pd_low_deinit();
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return ESP_ERR_NO_MEM;
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#endif
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}
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return ESP_OK;
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}
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esp_err_t esp_sleep_cpu_pd_low_deinit(void)
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{
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if (s_cpu_retention.retent.cpu_pd_mem) {
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heap_caps_free(s_cpu_retention.retent.cpu_pd_mem);
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s_cpu_retention.retent.cpu_pd_mem = NULL;
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}
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if (esp_sleep_tagmem_pd_low_deinit() != ESP_OK) {
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#ifdef CONFIG_ESP32S3_DATA_CACHE_16KB
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esp_sleep_cpu_pd_low_deinit();
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return ESP_ERR_NO_MEM;
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#endif
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}
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return ESP_OK;
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}
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void sleep_enable_cpu_retention(void)
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{
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rtc_cntl_hal_enable_cpu_retention(&s_cpu_retention.retent);
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rtc_cntl_hal_enable_tagmem_retention(&s_cpu_retention.retent);
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}
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void IRAM_ATTR sleep_disable_cpu_retention(void)
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{
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rtc_cntl_hal_disable_cpu_retention(&s_cpu_retention.retent);
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rtc_cntl_hal_disable_tagmem_retention(&s_cpu_retention.retent);
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}
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esp_err_t esp_sleep_cpu_retention_init(void)
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{
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return esp_sleep_cpu_pd_low_init();
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}
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esp_err_t esp_sleep_cpu_retention_deinit(void)
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{
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return esp_sleep_cpu_pd_low_deinit();
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}
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bool cpu_domain_pd_allowed(void)
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{
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return (s_cpu_retention.retent.cpu_pd_mem != NULL);
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}
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esp_err_t sleep_cpu_configure(bool light_sleep_enable)
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{
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#if ESP_SLEEP_POWER_DOWN_CPU
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if (light_sleep_enable) {
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ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_init(), TAG, "Failed to enable CPU power down during light sleep.");
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} else {
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ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_deinit(), TAG, "Failed to release CPU retention memory");
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}
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#endif
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return ESP_OK;
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}
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