kopia lustrzana https://github.com/espressif/esp-idf
322 wiersze
11 KiB
C
322 wiersze
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdio.h>
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#include <string.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "spi_flash.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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uint8_t mode;
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uint8_t cmd_bit_len;
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uint16_t cmd;
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uint32_t addr;
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uint8_t addr_bit_len;
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uint8_t dummy_bit_len;
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uint8_t data_bit_len;
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uint8_t cs_sel: 4;
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uint8_t is_pe: 4;
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} esp_rom_opiflash_cmd_t;
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typedef struct {
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uint8_t addr_bit_len;
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uint8_t dummy_bit_len;
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uint16_t cmd;
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uint8_t cmd_bit_len;
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uint8_t var_dummy_en;
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} esp_rom_opiflash_spi0rd_t;
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typedef struct {
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esp_rom_opiflash_cmd_t rdid;
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esp_rom_opiflash_cmd_t rdsr;
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esp_rom_opiflash_cmd_t wren;
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esp_rom_opiflash_cmd_t se;
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esp_rom_opiflash_cmd_t be64k;
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esp_rom_opiflash_cmd_t read;
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esp_rom_opiflash_cmd_t pp;
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esp_rom_opiflash_spi0rd_t cache_rd_cmd;
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} esp_rom_opiflash_def_t;
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typedef struct {
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uint16_t cmd; /*!< Command value */
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uint16_t cmdBitLen; /*!< Command byte length*/
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uint32_t *addr; /*!< Point to address value*/
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uint32_t addrBitLen; /*!< Address byte length*/
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uint32_t *txData; /*!< Point to send data buffer*/
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uint32_t txDataBitLen; /*!< Send data byte length.*/
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uint32_t *rxData; /*!< Point to recevie data buffer*/
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uint32_t rxDataBitLen; /*!< Recevie Data byte length.*/
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uint32_t dummyBitLen;
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} esp_rom_spi_cmd_t;
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#define ESP_ROM_OPIFLASH_MUX_TAKE()
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#define ESP_ROM_OPIFLASH_MUX_GIVE()
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#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0))
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#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1))
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// Definition of MX25UM25645G Octa Flash
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// SPI status register
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#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
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#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
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#define ESP_ROM_SPIFLASH_BP0 BIT2
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#define ESP_ROM_SPIFLASH_BP1 BIT3
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#define ESP_ROM_SPIFLASH_BP2 BIT4
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#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
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#define ESP_ROM_SPIFLASH_QE BIT9
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#define FLASH_OP_MODE_RDCMD_DOUT 0x3B
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#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000
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#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000
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#define ESP_ROM_FLASH_PAGE_SIZE 256
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// FLASH commands
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#define ROM_FLASH_CMD_RDID 0x9F
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#define ROM_FLASH_CMD_WRSR 0x01
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#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
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#define ROM_FLASH_CMD_WREN 0x06
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#define ROM_FLASH_CMD_WRDI 0x04
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#define ROM_FLASH_CMD_RDSR 0x05
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#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
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#define ROM_FLASH_CMD_ERASE_SEC 0x20
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#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52
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#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8
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#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */
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#define ROM_FLASH_CMD_RSTEN 0x66
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#define ROM_FLASH_CMD_RST 0x99
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#define ROM_FLASH_CMD_SE4B 0x21
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#define ROM_FLASH_CMD_SE4B_OCT 0xDE21
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#define ROM_FLASH_CMD_BE4B 0xDC
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#define ROM_FLASH_CMD_BE4B_OCT 0x23DC
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#define ROM_FLASH_CMD_RSTEN_OCT 0x9966
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#define ROM_FLASH_CMD_RST_OCT 0x6699
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#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC
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#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE
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#define ROM_FLASH_CMD_FSTRD4B 0x0C
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#define ROM_FLASH_CMD_PP4B 0x12
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#define ROM_FLASH_CMD_PP4B_OCT 0xED12
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#define ROM_FLASH_CMD_RDID_OCT 0x609F
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#define ROM_FLASH_CMD_WREN_OCT 0xF906
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#define ROM_FLASH_CMD_RDSR_OCT 0xFA05
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#define ROM_FLASH_CMD_RDCR2 0x71
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#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71
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#define ROM_FLASH_CMD_WRCR2 0x72
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#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72
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// Definitions for GigaDevice GD25LX256E Flash
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#define ROM_FLASH_CMD_RDFSR_GD 0x70
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#define ROM_FLASH_CMD_RD_GD 0x03
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#define ROM_FLASH_CMD_RD4B_GD 0x13
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#define ROM_FLASH_CMD_FSTRD_GD 0x0B
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#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C
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#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B
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#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C
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#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB
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#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC
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#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD
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#define ROM_FLASH_CMD_PP_GD 0x02
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#define ROM_FLASH_CMD_PP4B_GD 0x12
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#define ROM_FLASH_CMD_PP_OOUT_GD 0x82
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#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84
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#define ROM_FLASH_CMD_PP_OIO_GD 0xC2
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#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E
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#define ROM_FLASH_CMD_SE_GD 0x20
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#define ROM_FLASH_CMD_SE4B_GD 0x21
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#define ROM_FLASH_CMD_BE32K_GD 0x52
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#define ROM_FLASH_CMD_BE32K4B_GD 0x5C
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#define ROM_FLASH_CMD_BE64K_GD 0xD8
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#define ROM_FLASH_CMD_BE64K4B_GD 0xDC
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#define ROM_FLASH_CMD_EN4B_GD 0xB7
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#define ROM_FLASH_CMD_DIS4B_GD 0xE9
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extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def;
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/**
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* @brief init legacy driver for Octal Flash
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*/
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void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t *flash_cmd_def);
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// spi user mode command config
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/**
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* @brief Config the spi user command
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* @param spi_num spi port
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* @param pcmd pointer to accept the spi command struct
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*/
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void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd);
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/**
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* @brief Start a spi user command sequence
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* @param spi_num spi port
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* @param rx_buf buffer pointer to receive data
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* @param rx_len receive data length in byte
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* @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
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* @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission
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*/
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void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase);
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/**
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* @brief Config opi flash pads according to efuse settings.
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*/
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void esp_rom_opiflash_pin_config(void);
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// set SPI read/write mode
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/**
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* @brief Set SPI operation mode
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* @param spi_num spi port
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* @param mode Flash Read Mode
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*/
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void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
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/**
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* @brief Set data swap mode in DTR(DDR) mode
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* @param spi_num spi port
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* @param wr_swap to decide whether to swap fifo data in dtr write operation
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* @param rd_swap to decide whether to swap fifo data in dtr read operation
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*/
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void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap);
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/**
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* @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
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* @param spi_num spi port
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*/
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void esp_rom_opiflash_mode_reset(int spi_num);
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/**
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* @brief To execute a flash operation command
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* @param spi_num spi port
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* @param mode Flash Read Mode
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* @param cmd data to send in command field
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* @param cmd_bit_len bit length of command field
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* @param addr data to send in address field
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* @param addr_bit_len bit length of address field
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* @param dummy_bits bit length of dummy field
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* @param mosi_data data buffer to be sent in mosi field
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* @param mosi_bit_len bit length of data buffer to be sent in mosi field
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* @param miso_data data buffer to accept data in miso field
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* @param miso_bit_len bit length of data buffer to accept data in miso field
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* @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1
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* @param is_write_erase_operation to indicate whether this a write or erase flash operation
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*/
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void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len,
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uint32_t cs_mask,
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bool is_write_erase_operation);
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/**
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* @brief send reset command to opi flash
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* @param spi_num spi port
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* @param mode Flash Operation Mode
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*/
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void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode);
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/**
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* @brief to read opi flash ID
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* @note command format would be defined in initialization
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* @param[out] out_id buffer to accept id
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* @return flash operation result
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*/
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esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id);
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/**
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* @brief to read opi flash status register
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* @note command format would be defined in initialization
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* @return opi flash status value
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*/
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uint8_t esp_rom_opiflash_rdsr(void);
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/**
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* @brief wait opi flash status register to be idle
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* @note command format would be defined in initialization
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* @return flash operation result
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*/
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esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void);
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/**
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* @brief to erase flash sector
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* @note command format would be defined in initialization
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* @param sector_num the sector to be erased
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* @return flash operation result
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*/
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esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(uint32_t sector_num);
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/**
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* @brief to erase flash block
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* @note command format would be defined in initialization
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* @param block_num the block to be erased
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* @return flash operation result
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*/
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esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(uint32_t block_num);
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/**
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* @brief to erase a flash area define by start address and length
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* @note command format would be defined in initialization
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* @param start_addr the start address to be erased
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* @param area_len the erea length to be erased
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* @return flash operation result
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*/
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esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr, uint32_t area_len);
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/**
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* @brief to read data from opi flash
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* @note command format would be defined in initialization
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* @param flash_addr flash address to read data from
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* @param data_addr data buffer to accept the data
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* @param len data length to be read
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* @return flash operation result
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*/
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esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr, void *data_addr, int len);
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/**
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* @brief to write data to opi flash
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* @note command format would be defined in initialization
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* @param flash_addr flash address to write data to
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* @param data_addr data buffer to write to flash
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* @param len data length to write
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* @return flash operation result
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*/
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esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr, const uint32_t *data_addr, int len);
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/**
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* @brief send WREN command
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* @note command format would be defined in initialization
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* @param arg not used, set to NULL
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* @return flash operation result
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*/
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esp_rom_spiflash_result_t esp_rom_opiflash_wren(void* arg);
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/**
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* @brief to configure SPI0 read flash command format for cache
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* @note command format would be defined in initialization
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*
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*/
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void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache);
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esp_rom_spiflash_result_t esp_rom_opiflash_read_raw(uint32_t flash_addr, uint8_t* buf, int len);
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#ifdef __cplusplus
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}
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#endif
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