kopia lustrzana https://github.com/espressif/esp-idf
1192 wiersze
35 KiB
C
1192 wiersze
35 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for I2C register operations
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#pragma once
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#include "stdbool.h"
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#include "hal/misc.h"
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#include "hal/assert.h"
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#include "soc/i2c_periph.h"
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#include "soc/soc_caps.h"
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#include "soc/i2c_struct.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/system_struct.h"
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#include "hal/i2c_types.h"
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#include "esp_attr.h"
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#include "esp_assert.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief I2C hardware cmd register fields.
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*/
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typedef union {
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struct {
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uint32_t byte_num: 8, /*!< Specifies the length of data (in bytes) to be read or written */
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ack_en: 1, /*!< Used to enable the I2C controller during a write operation to check whether ACK */
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ack_exp: 1, /*!< Used to configure the level of the ACK bit expected by the I2C controller during a write operation */
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ack_val: 1, /*!< Used to configure the level of the ACK bit sent by the I2C controller during a read operation */
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op_code: 3, /*!< Indicates the command */
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reserved14: 17, /*!< Reserved bits */
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done: 1; /*!< Indicates that a command has been executed */
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};
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uint32_t val;
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} i2c_ll_hw_cmd_t;
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// I2C operation mode command
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#define I2C_LL_CMD_RESTART 6 /*!<I2C restart command */
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#define I2C_LL_CMD_WRITE 1 /*!<I2C write command */
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#define I2C_LL_CMD_READ 3 /*!<I2C read command */
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#define I2C_LL_CMD_STOP 2 /*!<I2C stop command */
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#define I2C_LL_CMD_END 4 /*!<I2C end command */
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typedef enum {
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I2C_INTR_MST_TXFIFO_WM = (1 << 1),
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I2C_INTR_MST_RXFIFO_WM = (1 << 0),
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I2C_LL_INTR_NACK = (1 << 10),
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I2C_LL_INTR_TIMEOUT = (1 << 8),
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I2C_LL_INTR_MST_COMPLETE = (1 << 7),
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I2C_LL_INTR_ARBITRATION = (1 << 5),
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I2C_LL_INTR_END_DETECT = (1 << 3),
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I2C_LL_INTR_ST_TO = (1 << 13),
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} i2c_ll_master_intr_t;
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typedef enum {
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I2C_INTR_SLV_TXFIFO_WM = (1 << 1),
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I2C_INTR_SLV_RXFIFO_WM = (1 << 0),
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I2C_INTR_SLV_COMPLETE = (1 << 7),
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I2C_INTR_START = (1 << 15),
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I2C_INTR_STRETCH = (1 << 16),
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} i2c_ll_slave_intr_t;
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// Get the I2C hardware instance
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#define I2C_LL_GET_HW(i2c_num) (((i2c_num) == 0) ? &I2C0 : &I2C1)
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#define I2C_LL_MASTER_EVENT_INTR (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
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#define I2C_LL_SLAVE_EVENT_INTR (I2C_TRANS_COMPLETE_INT_ENA_M|I2C_TXFIFO_WM_INT_ENA_M|I2C_RXFIFO_WM_INT_ENA_M | I2C_SLAVE_STRETCH_INT_ENA_M)
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#define I2C_LL_SLAVE_RX_EVENT_INTR (I2C_TRANS_COMPLETE_INT_ENA_M | I2C_RXFIFO_WM_INT_ENA_M | I2C_SLAVE_STRETCH_INT_ENA_M)
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#define I2C_LL_SLAVE_TX_EVENT_INTR (I2C_TXFIFO_WM_INT_ENA_M)
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#define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT (9)
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/**
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* @brief Calculate I2C bus frequency
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* Note that the clock accuracy is affected by the external pull-up resistor,
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* here we try to to calculate a configuration parameter which is close to the required clock.
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* But in I2C communication, the clock accuracy is not very concerned.
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*
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* @param source_clk I2C source clock
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* @param bus_freq I2C bus frequency
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* @param clk_cal Pointer to accept the clock configuration
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*
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* @return None
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*/
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static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_hal_clk_config_t *clk_cal)
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{
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uint32_t clkm_div = source_clk / (bus_freq * 1024) + 1;
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uint32_t sclk_freq = source_clk / clkm_div;
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uint32_t half_cycle = sclk_freq / bus_freq / 2;
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//SCL
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clk_cal->clkm_div = clkm_div;
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clk_cal->scl_low = half_cycle;
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// default, scl_wait_high < scl_high
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// Make 80KHz as a boundary here, because when working at lower frequency, too much scl_wait_high will faster the frequency
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// according to some hardware behaviors.
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clk_cal->scl_wait_high = (bus_freq >= 80 * 1000) ? (half_cycle / 2 - 2) : (half_cycle / 4);
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clk_cal->scl_high = half_cycle - clk_cal->scl_wait_high;
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clk_cal->sda_hold = half_cycle / 4;
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clk_cal->sda_sample = half_cycle / 2;
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clk_cal->setup = half_cycle;
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clk_cal->hold = half_cycle;
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//default we set the timeout value to about 10 bus cycles
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// log(20*half_cycle)/log(2) = log(half_cycle)/log(2) + log(20)/log(2)
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clk_cal->tout = (int)(sizeof(half_cycle) * 8 - __builtin_clz(5 * half_cycle)) + 2;
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/* Verify the assumptions made by the hardware */
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HAL_ASSERT(clk_cal->scl_wait_high < clk_cal->sda_sample &&
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clk_cal->sda_sample < clk_cal->scl_high);
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}
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/**
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* @brief Update I2C configuration
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_update(i2c_dev_t *hw)
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{
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hw->ctr.conf_upgate = 1;
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}
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/**
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* @brief Enable the bus clock for I2C module
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*
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* @param i2c_port I2C port id
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* @param enable true to enable, false to disable
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*/
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static inline void i2c_ll_enable_bus_clock(int i2c_port, bool enable)
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{
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if (i2c_port == 0) {
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SYSTEM.perip_clk_en0.i2c_ext0_clk_en = enable;
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} else if (i2c_port == 1) {
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SYSTEM.perip_clk_en0.i2c_ext1_clk_en = enable;
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define i2c_ll_enable_bus_clock(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i2c_ll_enable_bus_clock(__VA_ARGS__);} while(0)
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/**
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* @brief Reset the I2C module
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*
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* @param i2c_port Group ID
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*/
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static inline void i2c_ll_reset_register(int i2c_port)
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{
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if (i2c_port == 0) {
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SYSTEM.perip_rst_en0.i2c_ext0_rst = 1;
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SYSTEM.perip_rst_en0.i2c_ext0_rst = 0;
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} else if (i2c_port == 1) {
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SYSTEM.perip_rst_en0.i2c_ext1_rst = 1;
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SYSTEM.perip_rst_en0.i2c_ext1_rst = 0;
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define i2c_ll_reset_register(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i2c_ll_reset_register(__VA_ARGS__);} while(0)
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/**
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* @brief Configure the I2C bus timing related register.
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*
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* @param hw Beginning address of the peripheral registers
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* @param bus_cfg Pointer to the data structure holding the register configuration.
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*
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* @return None
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*/
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static inline void i2c_ll_master_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1);
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/* According to the Technical Reference Manual, the following timings must be subtracted by 1.
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* However, according to the practical measurement and some hardware behaviour, if wait_high_period and scl_high minus one.
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* The SCL frequency would be a little higher than expected. Therefore, the solution
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* here is not to minus scl_high as well as scl_wait high, and the frequency will be absolutely accurate to all frequency
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* to some extent. */
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hw->scl_low_period.scl_low_period = bus_cfg->scl_low - 1;
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hw->scl_high_period.scl_high_period = bus_cfg->scl_high;
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hw->scl_high_period.scl_wait_high_period = bus_cfg->scl_wait_high;
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//sda sample
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hw->sda_hold.sda_hold_time = bus_cfg->sda_hold - 1;
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hw->sda_sample.sda_sample_time = bus_cfg->sda_sample - 1;
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//setup
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hw->scl_rstart_setup.scl_rstart_setup_time = bus_cfg->setup - 1;
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hw->scl_stop_setup.scl_stop_setup_time = bus_cfg->setup - 1;
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//hold
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hw->scl_start_hold.scl_start_hold_time = bus_cfg->hold - 1;
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hw->scl_stop_hold.scl_stop_hold_time = bus_cfg->hold - 1;
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hw->to.time_out_value = bus_cfg->tout;
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hw->to.time_out_en = 1;
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}
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/**
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* @brief Set fractional divider
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*
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* @param hw Beginning address of the peripheral registers
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* @param div_a The denominator of the frequency divider factor of the i2c function clock
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* @param div_b The numerator of the frequency divider factor of the i2c function clock.
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*/
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static inline void i2c_ll_master_set_fractional_divider(i2c_dev_t *hw, uint8_t div_a, uint8_t div_b)
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{
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/* Set div_a and div_b to 0, as it's not necessary to use them */
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_a, div_a);
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_b, div_b);
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}
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/**
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* @brief Set fractional divider
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*
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* @param hw Beginning address of the peripheral registers
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* @param div_a The denominator of the frequency divider factor of the i2c function clock
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* @param div_b The numerator of the frequency divider factor of the i2c function clock.
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*/
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static inline void i2c_ll_master_get_fractional_divider(i2c_dev_t *hw, uint32_t *div_a, uint32_t *div_b)
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{
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/* Set div_a and div_b to 0, as it's not necessary to use them */
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*div_a = hw->clk_conf.sclk_div_a;
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*div_b = hw->clk_conf.sclk_div_b;
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}
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/**
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* @brief Get clock configurations from registers
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*
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* @param hw Beginning address of the peripheral registers
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* @param div_num div_num
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* @param clk_sel clk_sel
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* @param clk_active clk_active
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*/
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static inline void i2c_ll_master_save_clock_configurations(i2c_dev_t *hw, uint32_t *div_num, uint8_t *clk_sel, uint8_t *clk_active)
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{
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*div_num = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num);
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*clk_sel = hw->clk_conf.sclk_sel;
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*clk_active = hw->clk_conf.sclk_active;
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}
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/**
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* @brief Get clock configurations from registers
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*
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* @param hw Beginning address of the peripheral registers
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* @param div_num div_num
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* @param clk_sel clk_sel
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* @param clk_active clk_active
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*/
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static inline void i2c_ll_master_restore_clock_configurations(i2c_dev_t *hw, uint32_t div_num, uint8_t clk_sel, uint8_t clk_active)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, div_num);
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hw->clk_conf.sclk_sel = clk_sel;
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hw->clk_conf.sclk_active = clk_active;
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}
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/**
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* @brief Reset I2C txFIFO
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_txfifo_rst(i2c_dev_t *hw)
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{
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hw->fifo_conf.tx_fifo_rst = 1;
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hw->fifo_conf.tx_fifo_rst = 0;
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}
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/**
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* @brief Reset I2C rxFIFO
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_rxfifo_rst(i2c_dev_t *hw)
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{
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hw->fifo_conf.rx_fifo_rst = 1;
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hw->fifo_conf.rx_fifo_rst = 0;
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}
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/**
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* @brief Clear I2C interrupt status
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*
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* @param hw Beginning address of the peripheral registers
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* @param mask Interrupt mask needs to be cleared
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask)
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{
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hw->int_clr.val = mask;
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}
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/**
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* @brief Enable I2C interrupt
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*
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* @param hw Beginning address of the peripheral registers
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* @param mask Interrupt mask needs to be enabled
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask)
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{
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hw->int_ena.val |= mask;
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}
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/**
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* @brief Disable I2C interrupt
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*
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* @param hw Beginning address of the peripheral registers
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* @param mask Interrupt mask needs to be disabled
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask)
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{
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hw->int_ena.val &= (~mask);
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}
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/**
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* @brief Get I2C interrupt status
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return I2C interrupt status
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
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{
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*intr_status = hw->int_status.val;
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}
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/**
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* @brief Configure I2C memory access mode, FIFO mode or non-FIFO mode
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*
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* @param hw Beginning address of the peripheral registers
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* @param fifo_mode_en Set true to enable FIFO access mode, else, set it false
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*
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* @return None
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*/
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static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
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{
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hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
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}
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/**
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* @brief Configure I2C timeout
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*
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* @param hw Beginning address of the peripheral registers
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* @param tout_num The I2C timeout value needs to be set (2^tout in core clock cycle)
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*
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* @return None
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*/
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static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
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{
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hw->to.time_out_value = tout;
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}
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/**
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* @brief Configure I2C slave broadcasting mode.
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*
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* @param hw Beginning address of the peripheral registers
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* @param broadcast_en Set true to enable broadcast, else, set it false
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*
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* @return None
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*/
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static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_en)
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{
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hw->ctr.addr_broadcasting_en = broadcast_en;
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}
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/**
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* @brief Get the cause of SCL clock stretching in slave mode
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*
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* @param hw Beginning address of the peripheral registers
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* @param stretch_cause Pointer to stretch cause in the slave mode.
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
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{
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switch (hw->sr.stretch_cause) {
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case 0:
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*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
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break;
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case 1:
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*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_TX_EMPTY;
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break;
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case 2:
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*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_RX_FULL;
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break;
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case 3:
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*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_SENDING_ACK;
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break;
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default:
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HAL_ASSERT(false);
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break;
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}
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}
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/**
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* @brief Configure I2C slave address
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*
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* @param hw Beginning address of the peripheral registers
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* @param slave_addr I2C slave address needs to be set
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* @param addr_10bit_en Set true to enable 10-bit slave address mode, set false to enable 7-bit address mode
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*
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* @return None
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*/
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static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, bool addr_10bit_en)
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{
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hw->slave_addr.addr_10bit_en = addr_10bit_en;
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if (addr_10bit_en) {
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uint16_t addr_14_7 = (slave_addr & 0xff) << 7;
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uint8_t addr_6_0 = ((slave_addr & 0x300) >> 8) | 0x78;
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hw->slave_addr.slave_addr = addr_14_7 | addr_6_0;
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hw->ctr.addr_10bit_rw_check_en = addr_10bit_en;
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} else {
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hw->slave_addr.slave_addr = slave_addr;
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}
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}
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/**
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* @brief Write I2C hardware command register
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param cmd I2C hardware command
|
|
* @param cmd_idx The index of the command register, should be less than 16
|
|
*
|
|
* @return None
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline void i2c_ll_master_write_cmd_reg(i2c_dev_t *hw, i2c_ll_hw_cmd_t cmd, int cmd_idx)
|
|
{
|
|
hw->comd[cmd_idx].val = cmd.val;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure I2C start timing
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param start_setup The start condition setup period (in core clock cycle)
|
|
* @param start_hold The start condition hold period (in core clock cycle)
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_master_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold)
|
|
{
|
|
hw->scl_rstart_setup.scl_rstart_setup_time = start_setup;
|
|
hw->scl_start_hold.scl_start_hold_time = start_hold - 1;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure I2C stop timing
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param stop_setup The stop condition setup period (in core clock cycle)
|
|
* @param stop_hold The stop condition hold period (in core clock cycle)
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_master_set_stop_timing(i2c_dev_t *hw, int stop_setup, int stop_hold)
|
|
{
|
|
hw->scl_stop_setup.scl_stop_setup_time = stop_setup;
|
|
hw->scl_stop_hold.scl_stop_hold_time = stop_hold;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure I2C stop timing
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param sda_sample The SDA sample time (in core clock cycle)
|
|
* @param sda_hold The SDA hold time (in core clock cycle)
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_hold)
|
|
{
|
|
hw->sda_hold.sda_hold_time = sda_hold;
|
|
hw->sda_sample.sda_sample_time = sda_sample;
|
|
}
|
|
|
|
/**
|
|
* @brief Set I2C txFIFO empty threshold
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param empty_thr The txFIFO empty threshold
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
|
|
{
|
|
hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
|
|
}
|
|
|
|
/**
|
|
* @brief Set I2C rxFIFO full threshold
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param full_thr The rxFIFO full threshold
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
|
|
{
|
|
hw->fifo_conf.fifo_prt_en = 1;
|
|
hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
|
|
}
|
|
|
|
/**
|
|
* @brief Set the I2C data mode, LSB or MSB
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param tx_mode Tx data bit mode
|
|
* @param rx_mode Rx data bit mode
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_set_data_mode(i2c_dev_t *hw, i2c_trans_mode_t tx_mode, i2c_trans_mode_t rx_mode)
|
|
{
|
|
hw->ctr.tx_lsb_first = tx_mode;
|
|
hw->ctr.rx_lsb_first = rx_mode;
|
|
}
|
|
|
|
/**
|
|
* @brief Get I2C sda timing configuration
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param sda_sample Pointer to accept the SDA sample timing configuration
|
|
* @param sda_hold Pointer to accept the SDA hold timing configuration
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sda_hold)
|
|
{
|
|
*sda_hold = hw->sda_hold.sda_hold_time;
|
|
*sda_sample = hw->sda_sample.sda_sample_time;
|
|
}
|
|
|
|
/**
|
|
* @brief Get the I2C hardware version
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return The I2C hardware version
|
|
*/
|
|
static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw)
|
|
{
|
|
return hw->date.val;
|
|
}
|
|
|
|
/**
|
|
* @brief Check if the I2C bus is busy
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return True if I2C state machine is busy, else false will be returned
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline bool i2c_ll_is_bus_busy(i2c_dev_t *hw)
|
|
{
|
|
return hw->sr.bus_busy;
|
|
}
|
|
|
|
/**
|
|
* @brief Check if I2C is master mode
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return True if I2C is master mode, else false will be returned
|
|
*/
|
|
static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw)
|
|
{
|
|
return hw->ctr.ms_mode;
|
|
}
|
|
|
|
/**
|
|
* @brief Get the rxFIFO readable length
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return RxFIFO readable length
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
|
|
{
|
|
*length = hw->sr.rxfifo_cnt;
|
|
}
|
|
|
|
/**
|
|
* @brief Get I2C txFIFO writable length
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return TxFIFO writable length
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
|
|
{
|
|
*length = SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt;
|
|
}
|
|
|
|
/**
|
|
* @brief Get I2C timeout configuration
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return The I2C timeout value
|
|
*/
|
|
static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
|
|
{
|
|
*timeout = hw->to.time_out_value;
|
|
}
|
|
|
|
/**
|
|
* @brief Start I2C transfer
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return None
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
|
|
{
|
|
hw->ctr.trans_start = 1;
|
|
}
|
|
|
|
/**
|
|
* @brief Get I2C start timing configuration
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param setup_time Pointer to accept the start condition setup period
|
|
* @param hold_time Pointer to accept the start condition hold period
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time)
|
|
{
|
|
*setup_time = hw->scl_rstart_setup.scl_rstart_setup_time;
|
|
*hold_time = hw->scl_start_hold.scl_start_hold_time + 1;
|
|
}
|
|
|
|
/**
|
|
* @brief Get I2C stop timing configuration
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param setup_time Pointer to accept the stop condition setup period
|
|
* @param hold_time Pointer to accept the stop condition hold period
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *hold_time)
|
|
{
|
|
*setup_time = hw->scl_stop_setup.scl_stop_setup_time;
|
|
*hold_time = hw->scl_stop_hold.scl_stop_hold_time;
|
|
}
|
|
|
|
/**
|
|
* @brief Write the I2C hardware txFIFO
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param ptr Pointer to data buffer
|
|
* @param len Amount of data needs to be writen
|
|
*
|
|
* @return None.
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
|
|
{
|
|
for (int i = 0; i < len; i++) {
|
|
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Read the I2C hardware rxFIFO
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param ptr Pointer to data buffer
|
|
* @param len Amount of data needs read
|
|
*
|
|
* @return None
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
|
|
{
|
|
for (int i = 0; i < len; i++) {
|
|
ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->data, fifo_rdata);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Write the I2C hardware txFIFO
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param ram_offset Offset value of I2C RAM.
|
|
* @param ptr Pointer to data buffer
|
|
* @param len Amount of data needs to be writen
|
|
*/
|
|
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
|
{
|
|
for (int i = 0; i < len; i++) {
|
|
hw->txfifo_mem[i + ram_offset] = ptr[i];
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Read the I2C hardware ram
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param ram_offset Offset value of I2C RAM.
|
|
* @param ptr Pointer to data buffer
|
|
* @param len Amount of data needs read
|
|
*/
|
|
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
|
{
|
|
for (int i = 0; i < len; i++) {
|
|
ptr[i] = hw->rxfifo_mem[i + ram_offset];
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Get access to I2C RAM address directly
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param addr_wr_en Enable I2C ram address read and write
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
|
|
{
|
|
hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure I2C hardware filter
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param filter_num If the glitch period on the line is less than this value, it can be filtered out
|
|
* If `filter_num == 0`, the filter will be disabled
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_master_set_filter(i2c_dev_t *hw, uint8_t filter_num)
|
|
{
|
|
if (filter_num > 0) {
|
|
hw->filter_cfg.scl_filter_thres = filter_num;
|
|
hw->filter_cfg.sda_filter_thres = filter_num;
|
|
hw->filter_cfg.scl_filter_en = 1;
|
|
hw->filter_cfg.sda_filter_en = 1;
|
|
} else {
|
|
hw->filter_cfg.scl_filter_en = 0;
|
|
hw->filter_cfg.sda_filter_en = 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Get I2C hardware filter configuration
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return The hardware filter configuration
|
|
*/
|
|
static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
|
|
{
|
|
*filter_conf = hw->filter_cfg.scl_filter_thres;
|
|
}
|
|
|
|
/**
|
|
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
|
|
{
|
|
hw->ctr.fsm_rst = 1;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear I2C bus, when the slave is stuck in a deadlock and keeps pulling the bus low,
|
|
* master can controls the SCL bus to generate 9 CLKs.
|
|
*
|
|
* Note: The master cannot detect if deadlock happens, but when the scl_st_to interrupt is generated, a deadlock may occur.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
|
|
{
|
|
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
|
|
hw->scl_sp_conf.scl_rst_slv_en = 1;
|
|
hw->ctr.conf_upgate = 1;
|
|
}
|
|
|
|
/**
|
|
* @brief Set I2C source clock
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param src_clk Source clock of the I2C
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_clk)
|
|
{
|
|
hw->clk_conf.sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable I2C peripheral controller clock
|
|
*
|
|
* @param dev Peripheral instance address
|
|
* @param en True to enable, False to disable
|
|
*/
|
|
static inline void i2c_ll_enable_controller_clock(i2c_dev_t *hw, bool en)
|
|
{
|
|
hw->clk_conf.sclk_active = en;
|
|
}
|
|
|
|
/**
|
|
* @brief Init I2C master
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_master_init(i2c_dev_t *hw)
|
|
{
|
|
typeof(hw->ctr) ctrl_reg;
|
|
ctrl_reg.val = 0;
|
|
ctrl_reg.ms_mode = 1;
|
|
ctrl_reg.clk_en = 1;
|
|
ctrl_reg.sda_force_out = 1;
|
|
ctrl_reg.scl_force_out = 1;
|
|
hw->ctr.val = ctrl_reg.val;
|
|
}
|
|
|
|
/**
|
|
* @brief Init I2C slave
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_slave_init(i2c_dev_t *hw)
|
|
{
|
|
typeof(hw->ctr) ctrl_reg;
|
|
ctrl_reg.val = 0;
|
|
ctrl_reg.sda_force_out = 1;
|
|
ctrl_reg.scl_force_out = 1;
|
|
hw->ctr.val = ctrl_reg.val;
|
|
hw->fifo_conf.fifo_addr_cfg_en = 0;
|
|
}
|
|
|
|
/**
|
|
* @brief Set whether slave should auto start, or only start with start signal from master
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
|
|
*/
|
|
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
|
|
{
|
|
hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en;
|
|
}
|
|
|
|
/**
|
|
* @brief Get I2C interrupt status register address
|
|
*/
|
|
static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev)
|
|
{
|
|
return &dev->int_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable I2C slave clock stretch.
|
|
*
|
|
* @param dev Beginning address of the peripheral registers.
|
|
* @param enable true: Enable, false: Disable.
|
|
*/
|
|
static inline void i2c_ll_slave_enable_scl_stretch(i2c_dev_t *dev, bool enable)
|
|
{
|
|
dev->scl_stretch_conf.slave_scl_stretch_en = enable;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear I2C clock stretch status
|
|
*
|
|
* @param dev Beginning address of the peripheral registers
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
|
|
{
|
|
dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
|
|
}
|
|
|
|
/**
|
|
* @brief Check if i2c command is done.
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param cmd_idx The index of the command register, must be less than 8
|
|
*
|
|
* @return True if the `cmd_idx` command is done. Otherwise false.
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
|
|
{
|
|
return hw->comd[cmd_idx].command_done;
|
|
}
|
|
|
|
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
|
|
/////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
|
|
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// I2C master TX interrupt bitmap
|
|
#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
|
|
// I2C master RX interrupt bitmap
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#define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
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// I2C slave TX interrupt bitmap
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#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_WM_INT_ENA_M)
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// I2C slave RX interrupt bitmap
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#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
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// I2C max timeout value
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#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_VALUE_V
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#define I2C_LL_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */
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/**
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* @brief I2C interrupt event
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*/
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typedef enum {
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I2C_INTR_EVENT_ERR,
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I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */
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I2C_INTR_EVENT_NACK, /*!< I2C NACK event */
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I2C_INTR_EVENT_TOUT, /*!< I2C time out event */
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I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */
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I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */
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I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */
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I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */
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} i2c_intr_event_t;
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/**
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* @brief Get I2C SCL timing configuration
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*
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* @param hw Beginning address of the peripheral registers
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* @param high_period Pointer to accept the SCL high period
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* @param low_period Pointer to accept the SCL low period
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*
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* @return None
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*/
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static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, int *low_period, int *wait_high_period)
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{
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*high_period = hw->scl_high_period.scl_high_period;
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*wait_high_period = hw->scl_high_period.scl_wait_high_period;
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*low_period = hw->scl_low_period.scl_low_period;
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}
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/**
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* @brief Configure I2C SCL timing
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*
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* @param hw Beginning address of the peripheral registers
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* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
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* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
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* @param wait_high_period The I2C SCL wait rising edge period.
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*
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* @return None.
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*/
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static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int low_period, int wait_high_period)
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{
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hw->scl_low_period.scl_low_period = low_period;
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hw->scl_high_period.scl_high_period = high_period;
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hw->scl_high_period.scl_wait_high_period = wait_high_period;
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}
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/**
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* @brief Get I2C master interrupt event
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*
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* @param hw Beginning address of the peripheral registers
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* @param event Pointer to accept the interrupt event
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
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{
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typeof(hw->int_status) int_sts;
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int_sts.val = hw->int_status.val;
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if (int_sts.arbitration_lost_int_st) {
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*event = I2C_INTR_EVENT_ARBIT_LOST;
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} else if (int_sts.nack_int_st) {
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*event = I2C_INTR_EVENT_NACK;
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} else if (int_sts.time_out_int_st) {
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*event = I2C_INTR_EVENT_TOUT;
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} else if (int_sts.end_detect_int_st) {
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*event = I2C_INTR_EVENT_END_DET;
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} else if (int_sts.trans_complete_int_st) {
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*event = I2C_INTR_EVENT_TRANS_DONE;
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} else {
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*event = I2C_INTR_EVENT_ERR;
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}
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}
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/**
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* @brief Get I2C slave interrupt event
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*
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* @param hw Beginning address of the peripheral registers
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* @param event Pointer to accept the interrupt event
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
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{
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typeof(hw->int_status) int_sts;
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int_sts.val = hw->int_status.val;
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if (int_sts.txfifo_wm_int_st) {
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*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
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} else if (int_sts.trans_complete_int_st) {
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*event = I2C_INTR_EVENT_TRANS_DONE;
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} else if (int_sts.rxfifo_wm_int_st) {
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*event = I2C_INTR_EVENT_RXFIFO_FULL;
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} else {
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*event = I2C_INTR_EVENT_ERR;
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}
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}
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/**
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* @brief Enable I2C master TX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw)
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{
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hw->int_clr.val = UINT32_MAX;
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hw->int_ena.val = I2C_LL_MASTER_TX_INT;
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}
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/**
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* @brief Enable I2C master RX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw)
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{
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hw->int_clr.val = UINT32_MAX;
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hw->int_ena.val = I2C_LL_MASTER_RX_INT;
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}
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/**
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* @brief Disable I2C master TX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT);
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}
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/**
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* @brief Disable I2C master RX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT);
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}
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/**
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* @brief
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val |= 0x2;
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}
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/**
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* @brief Enable I2C slave RX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val |= I2C_LL_SLAVE_RX_INT;
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}
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/**
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|
* @brief Disable I2C slave TX interrupt
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*
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* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT);
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}
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/**
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|
* @brief Disable I2C slave RX interrupt
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*
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|
* @param hw Beginning address of the peripheral registers
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*
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* @return None
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*/
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static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
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{
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hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT);
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}
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|
|
/**
|
|
* @brief Configure I2C SCL timing
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
|
|
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
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*
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|
* @return None.
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*/
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static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int high_period, int low_period)
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{
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int high_period_output = high_period - 10; // The rising edge by open-drain output + internal pullup (about 50K) is slow
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hw->scl_low_period.scl_low_period = low_period - 1;
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hw->scl_high_period.scl_high_period = high_period_output;
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hw->scl_high_period.scl_wait_high_period = high_period - high_period_output;
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}
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|
|
/**
|
|
* @brief Get the I2C data mode
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|
*
|
|
* @param hw Beginning address of the peripheral registers
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|
* @param tx_mode Pointer to accept the received bytes mode
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|
* @param rx_mode Pointer to accept the sended bytes mode
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*
|
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* @return None
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*/
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|
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
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|
{
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|
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
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|
*rx_mode = (i2c_trans_mode_t)(hw->ctr.rx_lsb_first);
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}
|
|
|
|
/**
|
|
* @brief Get I2C SCL timing configuration
|
|
*
|
|
* @param hw Beginning address of the peripheral registers
|
|
* @param high_period Pointer to accept the SCL high period
|
|
* @param low_period Pointer to accept the SCL low period
|
|
*
|
|
* @return None
|
|
*/
|
|
static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *low_period)
|
|
{
|
|
*high_period = hw->scl_high_period.scl_high_period + hw->scl_high_period.scl_wait_high_period;
|
|
*low_period = hw->scl_low_period.scl_low_period + 1;
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|
}
|
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|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|