kopia lustrzana https://github.com/espressif/esp-idf
224 wiersze
8.5 KiB
C
224 wiersze
8.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* This file is a target specific for DAC DMA peripheral
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* Target: ESP32-S2
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* DAC DMA peripheral (data source): SPI3 (i.e. use SPI DMA to transmit data)
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* DAC DMA interrupt source: SPI3
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* DAC digital controller clock source: DIG_SARADC_CLK (root clock: APB or APLL)
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*/
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#include "sdkconfig.h"
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#include "esp_private/spi_common_internal.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/adc_share_hw_ctrl.h"
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#include "hal/spi_ll.h"
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#include "hal/dac_ll.h"
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#include "hal/adc_ll.h"
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#include "hal/hal_utils.h"
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#include "hal/clk_tree_ll.h"
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#include "soc/lldesc.h"
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#include "soc/soc.h"
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#include "soc/soc_caps.h"
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#include "../dac_priv_dma.h"
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#include "clk_ctrl_os.h"
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#if CONFIG_DAC_ENABLE_DEBUG_LOG
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// The local log level must be defined before including esp_log.h
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// Set the maximum log level for this source file
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#define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
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#endif
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#include "esp_check.h"
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#include "esp_attr.h"
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#define DAC_DMA_PERIPH_SPI_HOST SPI3_HOST
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typedef struct {
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void *periph_dev; /* DMA peripheral device address */
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uint32_t dma_chan;
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spi_dma_ctx_t *spi_dma_ctx; /* spi_dma context */
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intr_handle_t intr_handle; /* Interrupt handle */
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bool use_apll; /* Whether use APLL as digital controller clock source */
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} dac_dma_periph_spi_t;
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static dac_dma_periph_spi_t *s_ddp = NULL; // Static DAC DMA peripheral structure pointer
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static const char *TAG = "DAC_DMA";
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static uint32_t s_dac_set_apll_freq(uint32_t expt_freq)
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{
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/* Set APLL coefficients to the given frequency */
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uint32_t real_freq = 0;
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esp_err_t ret = periph_rtc_apll_freq_set(expt_freq, &real_freq);
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if (ret == ESP_ERR_INVALID_ARG) {
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return 0;
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}
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if (ret == ESP_ERR_INVALID_STATE) {
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ESP_LOGW(TAG, "APLL is occupied already, it is working at %"PRIu32" Hz", real_freq);
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}
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ESP_LOGD(TAG, "APLL expected frequency is %"PRIu32" Hz, real frequency is %"PRIu32" Hz", expt_freq, real_freq);
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return real_freq;
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}
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/**
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* @brief Calculate and set DAC data frequency
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* @note DAC clock shares clock divider with ADC, the clock source is APB or APLL on ESP32-S2
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* freq_hz = (source_clk / (clk_div + (b / a) + 1)) / interval
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* interval range: 1~4095
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* @param freq_hz DAC byte transmit frequency
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* @return
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* - ESP_OK config success
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* - ESP_ERR_INVALID_ARG invalid frequency
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*/
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static esp_err_t s_dac_dma_periph_set_clock(uint32_t freq_hz, bool is_apll)
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{
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/* Step 1: Determine the digital clock source frequency */
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uint32_t digi_ctrl_freq; // Digital controller clock
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if (is_apll) {
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/* Theoretical frequency range (due to the limitation of DAC, the maximum frequency may not reach):
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* CLK_LL_APLL_MAX_HZ: 119.24 Hz ~ 67.5 MHz
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* CLK_LL_APLL_MIN_HZ: 5.06 Hz ~ 2.65 MHz */
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digi_ctrl_freq = s_dac_set_apll_freq(freq_hz < 120 ? CLK_LL_APLL_MIN_HZ : CLK_LL_APLL_MAX_HZ);
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ESP_RETURN_ON_FALSE(digi_ctrl_freq, ESP_ERR_INVALID_ARG, TAG, "set APLL coefficients failed");
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} else {
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digi_ctrl_freq = APB_CLK_FREQ;
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}
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/* Step 2: Determine the interval */
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uint32_t total_div = digi_ctrl_freq / freq_hz;
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uint32_t interval;
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/* For the case that smaller than the minimum ADC controller division, the required frequency is too big */
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ESP_RETURN_ON_FALSE(total_div >= 2, ESP_ERR_INVALID_ARG, TAG, "the DAC frequency is too big");
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if (total_div < 256) { // For the case that smaller than the maximum ADC controller division
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/* Fix the interval to 1, the division is fully realized by the ADC controller clock divider */
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interval = 1;
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} else if (total_div < 8192) { // for the case that smaller than the maximum interval
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/* Set the interval to 'total_div / 2', fix the integer part of ADC controller clock division to 2 */
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interval = total_div / 2;
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} else {
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/* Fix the interval to 4095, */
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interval = 4095;
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}
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ESP_RETURN_ON_FALSE(interval * 256 > total_div, ESP_ERR_INVALID_ARG, TAG, "the DAC frequency is too small");
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/* Step 3: Calculate the coefficients of ADC digital controller divider */
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hal_utils_clk_info_t adc_clk_info = {
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.src_freq_hz = digi_ctrl_freq / interval,
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.exp_freq_hz = freq_hz,
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.max_integ = 257,
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.min_integ = 1,
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.max_fract = 64,
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};
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hal_utils_clk_div_t adc_clk_div = {};
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hal_utils_calc_clk_div_frac_accurate(&adc_clk_info, &adc_clk_div);
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/* Step 4: Set the clock coefficients */
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dac_ll_digi_clk_inv(true);
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dac_ll_digi_set_trigger_interval(interval); // secondary clock division
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adc_ll_digi_controller_clk_div(adc_clk_div.integer - 1, adc_clk_div.denominator, adc_clk_div.numerator);
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adc_ll_digi_clk_sel(is_apll ? ADC_DIGI_CLK_SRC_APLL : ADC_DIGI_CLK_SRC_DEFAULT);
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return ESP_OK;
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}
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esp_err_t dac_dma_periph_init(uint32_t freq_hz, bool is_alternate, bool is_apll)
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{
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#if CONFIG_DAC_ENABLE_DEBUG_LOG
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esp_log_level_set(TAG, ESP_LOG_DEBUG);
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#endif
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esp_err_t ret = ESP_OK;
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/* Acquire DMA peripheral */
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ESP_RETURN_ON_FALSE(spicommon_periph_claim(DAC_DMA_PERIPH_SPI_HOST, "dac_dma"), ESP_ERR_NOT_FOUND, TAG, "Failed to acquire DAC DMA peripheral");
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adc_apb_periph_claim();
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/* Allocate DAC DMA peripheral object */
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s_ddp = (dac_dma_periph_spi_t *)heap_caps_calloc(1, sizeof(dac_dma_periph_spi_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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ESP_GOTO_ON_FALSE(s_ddp, ESP_ERR_NO_MEM, err, TAG, "No memory for DAC DMA object");
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s_ddp->periph_dev = (void *)SPI_LL_GET_HW(DAC_DMA_PERIPH_SPI_HOST);
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if (is_apll) {
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periph_rtc_apll_acquire();
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s_ddp->use_apll = true;
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}
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/* When transmit alternately, twice frequency is needed to guarantee the convert frequency in one channel */
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uint32_t trans_freq_hz = freq_hz * (is_alternate ? 2 : 1);
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ESP_GOTO_ON_ERROR(s_dac_dma_periph_set_clock(trans_freq_hz, is_apll), err, TAG, "Failed to set clock of DMA peripheral");
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ESP_GOTO_ON_ERROR(spicommon_dma_chan_alloc(DAC_DMA_PERIPH_SPI_HOST, SPI_DMA_CH_AUTO, &s_ddp->spi_dma_ctx),
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err, TAG, "Failed to allocate dma peripheral channel");
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s_ddp->dma_chan = s_ddp->spi_dma_ctx->rx_dma_chan.chan_id;
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spi_ll_enable_intr(s_ddp->periph_dev, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_OUT_TOTAL_EOF);
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dac_ll_digi_set_convert_mode(is_alternate);
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return ret;
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err:
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dac_dma_periph_deinit();
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return ret;
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}
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esp_err_t dac_dma_periph_deinit(void)
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{
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ESP_RETURN_ON_FALSE(s_ddp->intr_handle == NULL, ESP_ERR_INVALID_STATE, TAG, "The interrupt is not deregistered yet");
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if (s_ddp->dma_chan) {
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ESP_RETURN_ON_ERROR(spicommon_dma_chan_free(s_ddp->spi_dma_ctx), TAG, "Failed to free dma peripheral channel");
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}
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ESP_RETURN_ON_FALSE(spicommon_periph_free(DAC_DMA_PERIPH_SPI_HOST), ESP_FAIL, TAG, "Failed to release DAC DMA peripheral");
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spi_ll_disable_intr(s_ddp->periph_dev, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_OUT_TOTAL_EOF);
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adc_apb_periph_free();
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if (s_ddp) {
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if (s_ddp->use_apll) {
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periph_rtc_apll_release();
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s_ddp->use_apll = false;
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}
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free(s_ddp);
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s_ddp = NULL;
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}
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return ESP_OK;
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}
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int dac_dma_periph_get_intr_signal(void)
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{
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return spicommon_irqdma_source_for_host(DAC_DMA_PERIPH_SPI_HOST);
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}
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static void s_dac_dma_periph_reset(void)
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{
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spi_dma_ll_tx_reset(s_ddp->periph_dev, s_ddp->dma_chan);
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spi_ll_dma_tx_fifo_reset(s_ddp->periph_dev);
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}
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void dac_dma_periph_enable(void)
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{
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s_dac_dma_periph_reset();
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dac_ll_digi_trigger_output(true);
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}
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void dac_dma_periph_disable(void)
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{
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s_dac_dma_periph_reset();
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spi_dma_ll_tx_stop(s_ddp->periph_dev, s_ddp->dma_chan);
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dac_ll_digi_trigger_output(false);
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}
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uint32_t IRAM_ATTR dac_dma_periph_intr_is_triggered(void)
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{
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uint32_t ret = 0;
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ret |= spi_ll_get_intr(s_ddp->periph_dev, SPI_LL_INTR_OUT_EOF) ? DAC_DMA_EOF_INTR : 0;
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ret |= spi_ll_get_intr(s_ddp->periph_dev, SPI_LL_INTR_OUT_TOTAL_EOF) ? DAC_DMA_TEOF_INTR : 0;
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spi_ll_clear_intr(s_ddp->periph_dev, SPI_LL_INTR_OUT_EOF);
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spi_ll_clear_intr(s_ddp->periph_dev, SPI_LL_INTR_OUT_TOTAL_EOF);
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return ret;
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}
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uint32_t IRAM_ATTR dac_dma_periph_intr_get_eof_desc(void)
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{
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return spi_dma_ll_get_out_eof_desc_addr(s_ddp->periph_dev, s_ddp->dma_chan);
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}
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void dac_dma_periph_dma_trans_start(uint32_t desc_addr)
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{
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spi_dma_ll_tx_reset(s_ddp->periph_dev, s_ddp->dma_chan);
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spi_ll_dma_tx_fifo_reset(s_ddp->periph_dev);
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spi_dma_ll_tx_start(s_ddp->periph_dev, s_ddp->dma_chan, (lldesc_t *)desc_addr);
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}
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