kopia lustrzana https://github.com/espressif/esp-idf
349 wiersze
10 KiB
C
349 wiersze
10 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*******************************************************************************
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* NOTICE
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* The ll is not public api, don't use in application code.
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* See readme.md in soc/include/hal/readme.md
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******************************************************************************/
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// The Lowlevel layer for SPI Flash
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#pragma once
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#include <stdlib.h>
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#include "soc/spi_periph.h"
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#include "hal/spi_types.h"
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#include "hal/spi_flash_types.h"
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#include <sys/param.h> // For MIN/MAX
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#include <stdbool.h>
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#include <string.h>
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//Supported clock register values
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#define SPI_FLASH_LL_CLKREG_VAL_5MHZ ((spi_flash_ll_clock_reg_t){.val=0x0000F1CF}) ///< Clock set to 5 MHz
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#define SPI_FLASH_LL_CLKREG_VAL_10MHZ ((spi_flash_ll_clock_reg_t){.val=0x000070C7}) ///< Clock set to 10 MHz
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#define SPI_FLASH_LL_CLKREG_VAL_20MHZ ((spi_flash_ll_clock_reg_t){.val=0x00003043}) ///< Clock set to 20 MHz
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#define SPI_FLASH_LL_CLKREG_VAL_26MHZ ((spi_flash_ll_clock_reg_t){.val=0x00002002}) ///< Clock set to 26 MHz
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#define SPI_FLASH_LL_CLKREG_VAL_40MHZ ((spi_flash_ll_clock_reg_t){.val=0x00001001}) ///< Clock set to 40 MHz
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#define SPI_FLASH_LL_CLKREG_VAL_80MHZ ((spi_flash_ll_clock_reg_t){.val=0x80000000}) ///< Clock set to 80 MHz
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/// Get the start address of SPI peripheral registers by the host ID
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#define spi_flash_ll_get_hw(host_id) ((host_id)==SPI1_HOST? &SPI1:((host_id)==SPI2_HOST?&SPI2:((host_id)==SPI3_HOST?&SPI3:({abort();(spi_dev_t*)0;}))))
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/// type to store pre-calculated register value in above layers
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typedef typeof(SPI1.clock) spi_flash_ll_clock_reg_t;
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/*------------------------------------------------------------------------------
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* Control
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*----------------------------------------------------------------------------*/
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/**
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* Reset peripheral registers before configuration and starting control
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*
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* @param dev Beginning address of the peripheral registers.
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*/
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static inline void spi_flash_ll_reset(spi_dev_t *dev)
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{
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dev->user.val = 0;
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dev->ctrl.val = 0;
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}
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/**
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* Check whether the previous operation is done.
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*
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* @param dev Beginning address of the peripheral registers.
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*
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* @return true if last command is done, otherwise false.
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*/
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static inline bool spi_flash_ll_cmd_is_done(const spi_dev_t *dev)
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{
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return (dev->cmd.val == 0);
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}
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/**
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* Erase the flash chip.
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*
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* @param dev Beginning address of the peripheral registers.
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*/
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static inline void spi_flash_ll_erase_chip(spi_dev_t *dev)
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{
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dev->cmd.flash_ce = 1;
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}
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/**
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* Erase the sector, the address should be set by spi_flash_ll_set_address.
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*
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* @param dev Beginning address of the peripheral registers.
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*/
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static inline void spi_flash_ll_erase_sector(spi_dev_t *dev)
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{
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dev->ctrl.val = 0;
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dev->cmd.flash_se = 1;
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}
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/**
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* Erase the block, the address should be set by spi_flash_ll_set_address.
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*
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* @param dev Beginning address of the peripheral registers.
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*/
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static inline void spi_flash_ll_erase_block(spi_dev_t *dev)
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{
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dev->cmd.flash_be = 1;
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}
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/**
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* Enable/disable write protection for the flash chip.
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*
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* @param dev Beginning address of the peripheral registers.
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* @param wp true to enable the protection, false to disable (write enable).
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*/
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static inline void spi_flash_ll_set_write_protect(spi_dev_t *dev, bool wp)
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{
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if (wp) {
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dev->cmd.flash_wrdi = 1;
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} else {
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dev->cmd.flash_wren = 1;
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}
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}
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/**
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* Get the read data from the buffer after ``spi_flash_ll_read`` is done.
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*
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* @param dev Beginning address of the peripheral registers.
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* @param buffer Buffer to hold the output data
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* @param read_len Length to get out of the buffer
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*/
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static inline void spi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
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{
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if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
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// If everything is word-aligned, do a faster memcpy
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memcpy(buffer, (void *)dev->data_buf, read_len);
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} else {
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// Otherwise, slow(er) path copies word by word
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int copy_len = read_len;
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for (int i = 0; i < (read_len + 3) / 4; i++) {
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int word_len = MIN(sizeof(uint32_t), copy_len);
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uint32_t word = dev->data_buf[i];
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memcpy(buffer, &word, word_len);
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buffer = (void *)((intptr_t)buffer + word_len);
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copy_len -= word_len;
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}
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}
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}
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/**
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* Write a word to the data buffer.
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*
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* @param dev Beginning address of the peripheral registers.
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* @param word Data to write at address 0.
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*/
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static inline void spi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
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{
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dev->data_buf[0] = word;
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}
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/**
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* Program a page of the flash chip. Call ``spi_flash_ll_set_address`` before
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* this to set the address to program.
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*
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* @param dev Beginning address of the peripheral registers.
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* @param buffer Buffer holding the data to program
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* @param length Length to program.
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*/
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static inline void spi_flash_ll_program_page(spi_dev_t *dev, const void *buffer, uint32_t length)
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{
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dev->user.usr_dummy = 0;
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// Load data registers, word at a time
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int num_words = (length + 3) / 4;
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for (int i = 0; i < num_words; i++) {
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uint32_t word = 0;
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uint32_t word_len = MIN(length, sizeof(word));
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memcpy(&word, buffer, word_len);
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dev->data_buf[i] = word;
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length -= word_len;
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buffer = (void *)((intptr_t)buffer + word_len);
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}
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dev->cmd.flash_pp = 1;
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}
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/**
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* Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases,
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* should be configured before this is called.
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*
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* @param dev Beginning address of the peripheral registers.
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*/
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static inline void spi_flash_ll_user_start(spi_dev_t *dev)
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{
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dev->cmd.usr = 1;
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}
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/**
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* Check whether the host is idle to perform new commands.
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*
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* @param dev Beginning address of the peripheral registers.
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*
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* @return true if the host is idle, otherwise false
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*/
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static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev)
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{
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return dev->ext2.st != 0;
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}
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/*------------------------------------------------------------------------------
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* Configs
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*----------------------------------------------------------------------------*/
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/**
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* Select which pin to use for the flash
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*
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* @param dev Beginning address of the peripheral registers.
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* @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
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*/
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static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
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{
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dev->pin.cs0_dis = (pin == 0) ? 0 : 1;
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dev->pin.cs1_dis = (pin == 1) ? 0 : 1;
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dev->pin.cs2_dis = (pin == 2) ? 0 : 1;
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}
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/**
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* Set the read io mode.
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*
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* @param dev Beginning address of the peripheral registers.
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* @param read_mode I/O mode to use in the following transactions.
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*/
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static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
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{
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typeof (dev->ctrl) ctrl = dev->ctrl;
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ctrl.val &= ~(SPI_FREAD_QIO_M | SPI_FREAD_QUAD_M | SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M);
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ctrl.val |= SPI_FASTRD_MODE_M;
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switch (read_mode) {
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case SPI_FLASH_FASTRD:
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//the default option
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break;
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case SPI_FLASH_QIO:
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ctrl.fread_qio = 1;
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break;
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case SPI_FLASH_QOUT:
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ctrl.fread_quad = 1;
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break;
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case SPI_FLASH_DIO:
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ctrl.fread_dio = 1;
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break;
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case SPI_FLASH_DOUT:
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ctrl.fread_dual = 1;
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break;
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case SPI_FLASH_SLOWRD:
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ctrl.fastrd_mode = 0;
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break;
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default:
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abort();
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}
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dev->ctrl = ctrl;
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}
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/**
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* Set clock frequency to work at.
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*
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* @param dev Beginning address of the peripheral registers.
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* @param clock_val pointer to the clock value to set
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*/
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static inline void spi_flash_ll_set_clock(spi_dev_t *dev, spi_flash_ll_clock_reg_t *clock_val)
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{
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dev->clock = *clock_val;
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}
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/**
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* Set the input length, in bits.
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*
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* @param dev Beginning address of the peripheral registers.
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* @param bitlen Length of input, in bits.
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*/
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static inline void spi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
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{
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dev->user.usr_miso = bitlen > 0;
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dev->miso_dlen.usr_miso_dbitlen = bitlen ? (bitlen - 1) : 0;
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}
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/**
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* Set the output length, in bits (not including command, address and dummy
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* phases)
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*
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* @param dev Beginning address of the peripheral registers.
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* @param bitlen Length of output, in bits.
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*/
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static inline void spi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
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{
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dev->user.usr_mosi = bitlen > 0;
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dev->mosi_dlen.usr_mosi_dbitlen = bitlen ? (bitlen - 1) : 0;
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}
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/**
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* Set the command with fixed length (8 bits).
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*
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* @param dev Beginning address of the peripheral registers.
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* @param command Command to send
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*/
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static inline void spi_flash_ll_set_command8(spi_dev_t *dev, uint8_t command)
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{
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dev->user.usr_command = 1;
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typeof(dev->user2) user2 = {
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.usr_command_value = command,
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.usr_command_bitlen = (8 - 1),
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};
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dev->user2 = user2;
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}
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/**
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* Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write...
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*
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* @param dev Beginning address of the peripheral registers.
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* @param bitlen Length of the address, in bits
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*/
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static inline void spi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen)
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{
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dev->user1.usr_addr_bitlen = (bitlen - 1);
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dev->user.usr_addr = bitlen ? 1 : 0;
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}
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/**
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* Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
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*
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* @param dev Beginning address of the peripheral registers.
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* @param addr Address to send
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*/
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static inline void spi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
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{
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dev->addr = addr;
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}
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/**
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* Set the length of dummy cycles.
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*
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* @param dev Beginning address of the peripheral registers.
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* @param dummy_n Cycles of dummy phases
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*/
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static inline void spi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
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{
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dev->user.usr_dummy = dummy_n ? 1 : 0;
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dev->user1.usr_dummy_cyclelen = dummy_n - 1;
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}
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static inline void spi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
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{
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dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
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dev->ctrl2.setup_time = cs_setup_time - 1;
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}
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