kopia lustrzana https://github.com/espressif/esp-idf
90 wiersze
3.7 KiB
C
90 wiersze
3.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief I2S controller port number, the max port number is (SOC_I2S_NUM -1).
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*/
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typedef enum {
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I2S_NUM_0 = 0, /*!< I2S controller port 0 */
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#if SOC_I2S_NUM > 1
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I2S_NUM_1 = 1, /*!< I2S controller port 1 */
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#endif
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I2S_NUM_AUTO, /*!< Select whichever port is available */
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} i2s_port_t;
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/**
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* @brief I2S controller communication mode
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*/
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typedef enum {
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I2S_COMM_MODE_STD, /*!< I2S controller using standard communication mode, support Philips/MSB/PCM format */
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#if SOC_I2S_SUPPORTS_PDM
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I2S_COMM_MODE_PDM, /*!< I2S controller using PDM communication mode, support PDM output or input */
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#endif
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#if SOC_I2S_SUPPORTS_TDM
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I2S_COMM_MODE_TDM, /*!< I2S controller using TDM communication mode, support up to 16 slots per frame */
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#endif
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I2S_COMM_MODE_NONE, /*!< Unspecified I2S controller mode */
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} i2s_comm_mode_t;
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/**
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* @brief The multiple of MCLK to sample rate
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* @note MCLK is the minimum resolution of the I2S clock.
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* Increasing mclk multiple can reduce the clock jitter of BCLK and WS,
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* which is also useful for the codec that don't require MCLK but have strict requirement to BCLK.
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* For the 24-bit slot width, please choose a multiple that can be divided by 3 (i.e. 24-bit compatible).
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*/
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typedef enum {
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I2S_MCLK_MULTIPLE_128 = 128, /*!< MCLK = sample_rate * 128 */
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I2S_MCLK_MULTIPLE_192 = 192, /*!< MCLK = sample_rate * 192 (24-bit compatible) */
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I2S_MCLK_MULTIPLE_256 = 256, /*!< MCLK = sample_rate * 256 */
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I2S_MCLK_MULTIPLE_384 = 384, /*!< MCLK = sample_rate * 384 (24-bit compatible) */
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I2S_MCLK_MULTIPLE_512 = 512, /*!< MCLK = sample_rate * 512 */
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I2S_MCLK_MULTIPLE_576 = 576, /*!< MCLK = sample_rate * 576 (24-bit compatible) */
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I2S_MCLK_MULTIPLE_768 = 768, /*!< MCLK = sample_rate * 768 (24-bit compatible) */
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I2S_MCLK_MULTIPLE_1024 = 1024, /*!< MCLK = sample_rate * 1024 */
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I2S_MCLK_MULTIPLE_1152 = 1152, /*!< MCLK = sample_rate * 1152 (24-bit compatible) */
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} i2s_mclk_multiple_t;
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/**
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* @brief Event structure used in I2S event queue
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*/
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typedef struct {
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void *data; /**< The pointer of DMA buffer that just finished sending or receiving for `on_recv` and `on_sent` callback
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* NULL for `on_recv_q_ovf` and `on_send_q_ovf` callback
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*/
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size_t size; /**< The buffer size of DMA buffer when success to send or receive,
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* also the buffer size that dropped when queue overflow.
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* It is related to the dma_frame_num and data_bit_width, typically it is fixed when data_bit_width is not changed.
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*/
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} i2s_event_data_t;
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typedef struct i2s_channel_obj_t *i2s_chan_handle_t; /*!< I2S channel object handle, the control unit of the I2S driver*/
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/**
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* @brief I2S event callback
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* @param[in] handle I2S channel handle, created from `i2s_new_channel()`
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* @param[in] event I2S event data
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* @param[in] user_ctx User registered context, passed from `i2s_channel_register_event_callback()`
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*
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* @return Whether a high priority task has been waken up by this callback function
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*/
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typedef bool (*i2s_isr_callback_t)(i2s_chan_handle_t handle, i2s_event_data_t *event, void *user_ctx);
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#ifdef __cplusplus
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}
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#endif
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