kopia lustrzana https://github.com/espressif/esp-idf
350 wiersze
13 KiB
C
350 wiersze
13 KiB
C
/*
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* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "sys/param.h"
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#include "esp_timer_impl.h"
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#include "esp_timer.h"
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#include "esp_err.h"
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#include "esp_system.h"
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#include "esp_task.h"
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#include "esp_attr.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_private/esp_clk.h"
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#include "esp_private/periph_ctrl.h"
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#include "soc/soc.h"
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#include "soc/timer_group_reg.h"
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#include "soc/rtc.h"
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#include "hal/timer_ll.h"
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#include "freertos/FreeRTOS.h"
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/**
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* @file esp_timer_lac.c
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* @brief Implementation of chip-specific part of esp_timer
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*
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* This implementation uses TG0 LAC timer of the ESP32. This timer is
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* a 64-bit up-counting timer, with a programmable compare value (called 'alarm'
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* hereafter). When the timer reaches compare value, interrupt is raised.
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* The timer can be configured to produce an edge or a level interrupt.
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*/
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/* Selects which Timer Group peripheral to use */
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#define LACT_MODULE 0
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#if LACT_MODULE == 0
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#define INTR_SOURCE_LACT ETS_TG0_LACT_LEVEL_INTR_SOURCE
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#define PERIPH_LACT PERIPH_TIMG0_MODULE
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#elif LACT_MODULE == 1
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#define INTR_SOURCE_LACT ETS_TG1_LACT_LEVEL_INTR_SOURCE
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#define PERIPH_LACT PERIPH_TIMG1_MODULE
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#else
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#error "Incorrect the number of LACT module (only 0 or 1)"
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#endif
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/* Desired number of timer ticks per microsecond.
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* This value should be small enough so that all possible APB frequencies
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* could be divided by it without remainder.
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* On the other hand, the smaller this value is, the longer we need to wait
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* after setting UPDATE_REG before the timer value can be read.
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* If TICKS_PER_US == 1, then we need to wait up to 1 microsecond, which
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* makes esp_timer_impl_get_time function take too much time.
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* The value TICKS_PER_US == 2 allows for most of the APB frequencies, and
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* allows reading the counter quickly enough.
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*/
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#define TICKS_PER_US 2
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/* Shorter register names, used in this file */
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#define CONFIG_REG (TIMG_LACTCONFIG_REG(LACT_MODULE))
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#define RTC_STEP_REG (TIMG_LACTRTC_REG(LACT_MODULE))
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#define ALARM_LO_REG (TIMG_LACTALARMLO_REG(LACT_MODULE))
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#define ALARM_HI_REG (TIMG_LACTALARMHI_REG(LACT_MODULE))
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#define COUNT_LO_REG (TIMG_LACTLO_REG(LACT_MODULE))
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#define COUNT_HI_REG (TIMG_LACTHI_REG(LACT_MODULE))
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#define UPDATE_REG (TIMG_LACTUPDATE_REG(LACT_MODULE))
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#define LOAD_REG (TIMG_LACTLOAD_REG(LACT_MODULE))
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#define LOAD_LO_REG (TIMG_LACTLOADLO_REG(LACT_MODULE))
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#define LOAD_HI_REG (TIMG_LACTLOADHI_REG(LACT_MODULE))
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#define INT_ENA_REG (TIMG_INT_ENA_TIMERS_REG(LACT_MODULE))
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#define INT_ST_REG (TIMG_INT_ST_TIMERS_REG(LACT_MODULE))
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#define INT_CLR_REG (TIMG_INT_CLR_TIMERS_REG(LACT_MODULE))
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/* Helper type to convert between a 64-bit value and a pair of 32-bit values without shifts and masks */
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typedef struct {
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union {
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struct {
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uint32_t lo;
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uint32_t hi;
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};
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uint64_t val;
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};
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} timer_64b_reg_t;
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static const char* TAG = "esp_timer_impl";
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#define NOT_USED 0xBAD00FAD
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/* Interrupt handle returned by the interrupt allocator */
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#ifdef CONFIG_ESP_TIMER_ISR_AFFINITY_NO_AFFINITY
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#define ISR_HANDLERS (CONFIG_FREERTOS_NUMBER_OF_CORES)
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#else
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#define ISR_HANDLERS (1)
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#endif
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static intr_handle_t s_timer_interrupt_handle[ISR_HANDLERS] = { NULL };
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/* Function from the upper layer to be called when the interrupt happens.
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* Registered in esp_timer_impl_init.
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*/
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static intr_handler_t s_alarm_handler = NULL;
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/* Spinlock used to protect access to the hardware registers. */
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extern portMUX_TYPE s_time_update_lock;
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/* Alarm values to generate interrupt on match */
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extern uint64_t timestamp_id[2];
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uint64_t IRAM_ATTR esp_timer_impl_get_counter_reg(void)
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{
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uint32_t lo, hi;
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uint32_t lo_start = REG_READ(COUNT_LO_REG);
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uint32_t div = REG_GET_FIELD(CONFIG_REG, TIMG_LACT_DIVIDER);
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/* The peripheral doesn't have a bit to indicate that the update is done, so we poll the
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* lower 32 bit part of the counter until it changes, or a timeout expires.
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*/
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REG_WRITE(UPDATE_REG, 1);
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do {
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lo = REG_READ(COUNT_LO_REG);
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} while (lo == lo_start && div-- > 0);
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/* Since this function is called without a critical section, verify that LO and HI
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* registers are consistent. That is, if an interrupt happens between reading LO and
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* HI registers, and esp_timer_impl_get_time is called from an ISR, then try to
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* detect this by the change in LO register value, and re-read both registers.
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*/
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do {
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lo_start = lo;
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hi = REG_READ(COUNT_HI_REG);
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lo = REG_READ(COUNT_LO_REG);
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} while (lo != lo_start);
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timer_64b_reg_t result = {
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.lo = lo,
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.hi = hi
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};
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return result.val;
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}
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int64_t IRAM_ATTR esp_timer_impl_get_time(void)
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{
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return esp_timer_impl_get_counter_reg() / TICKS_PER_US;
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}
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int64_t esp_timer_get_time(void) __attribute__((alias("esp_timer_impl_get_time")));
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void IRAM_ATTR esp_timer_impl_set_alarm_id(uint64_t timestamp, unsigned alarm_id)
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{
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assert(alarm_id < sizeof(timestamp_id) / sizeof(timestamp_id[0]));
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portENTER_CRITICAL_SAFE(&s_time_update_lock);
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timestamp_id[alarm_id] = timestamp;
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timestamp = MIN(timestamp_id[0], timestamp_id[1]);
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if (timestamp != UINT64_MAX) {
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int64_t offset = TICKS_PER_US * 2;
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uint64_t now_time = esp_timer_impl_get_counter_reg();
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timer_64b_reg_t alarm = { .val = MAX(timestamp * TICKS_PER_US, now_time + offset) };
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do {
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REG_CLR_BIT(CONFIG_REG, TIMG_LACT_ALARM_EN);
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REG_WRITE(ALARM_LO_REG, alarm.lo);
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REG_WRITE(ALARM_HI_REG, alarm.hi);
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REG_SET_BIT(CONFIG_REG, TIMG_LACT_ALARM_EN);
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now_time = esp_timer_impl_get_counter_reg();
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int64_t delta = (int64_t)alarm.val - (int64_t)now_time;
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if (delta <= 0 && REG_GET_FIELD(INT_ST_REG, TIMG_LACT_INT_ST) == 0) {
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// new alarm is less than the counter and the interrupt flag is not set
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offset += llabs(delta) + TICKS_PER_US * 2;
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alarm.val = now_time + offset;
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} else {
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// finish if either (alarm > counter) or the interrupt flag is already set.
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break;
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}
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} while (1);
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}
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portEXIT_CRITICAL_SAFE(&s_time_update_lock);
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}
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static void IRAM_ATTR timer_alarm_isr(void *arg)
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{
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#if ISR_HANDLERS == 1
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/* Clear interrupt status */
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REG_WRITE(INT_CLR_REG, TIMG_LACT_INT_CLR);
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/* Call the upper layer handler */
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(*s_alarm_handler)(arg);
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#else
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static volatile uint32_t processed_by = NOT_USED;
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static volatile bool pending_alarm = false;
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/* CRITICAL section ensures the read/clear is atomic between cores */
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portENTER_CRITICAL_ISR(&s_time_update_lock);
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if (REG_GET_FIELD(INT_ST_REG, TIMG_LACT_INT_ST)) {
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// Clear interrupt status
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REG_WRITE(INT_CLR_REG, TIMG_LACT_INT_CLR);
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// Is the other core already processing a previous alarm?
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if (processed_by == NOT_USED) {
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// Current core is not processing an alarm yet
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processed_by = xPortGetCoreID();
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do {
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pending_alarm = false;
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// Clear interrupt status
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REG_WRITE(INT_CLR_REG, TIMG_LACT_INT_CLR);
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portEXIT_CRITICAL_ISR(&s_time_update_lock);
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(*s_alarm_handler)(arg);
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portENTER_CRITICAL_ISR(&s_time_update_lock);
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// Another alarm could have occurred while were handling the previous alarm.
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// Check if we need to call the s_alarm_handler again:
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// 1) if the alarm has already been fired, it helps to handle it immediately without an additional ISR call.
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// 2) handle pending alarm that was cleared by the other core in time when this core worked with the current alarm.
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} while (REG_GET_FIELD(INT_ST_REG, TIMG_LACT_INT_ST) || pending_alarm);
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processed_by = NOT_USED;
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} else {
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// Current core arrived at ISR but the other core is still handling a previous alarm.
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// Once we already cleared the ISR status we need to let the other core know that it was.
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// Set the flag to handle the current alarm by the other core later.
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pending_alarm = true;
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}
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}
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portEXIT_CRITICAL_ISR(&s_time_update_lock);
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#endif // ISR_HANDLERS != 1
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}
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void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us)
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{
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portENTER_CRITICAL(&s_time_update_lock);
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assert(apb_ticks_per_us >= 3 && "divider value too low");
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assert(apb_ticks_per_us % TICKS_PER_US == 0 && "APB frequency (in MHz) should be divisible by TICK_PER_US");
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REG_SET_FIELD(CONFIG_REG, TIMG_LACT_DIVIDER, apb_ticks_per_us / TICKS_PER_US);
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portEXIT_CRITICAL(&s_time_update_lock);
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}
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void esp_timer_impl_set(uint64_t new_us)
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{
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portENTER_CRITICAL(&s_time_update_lock);
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timer_64b_reg_t dst = { .val = new_us * TICKS_PER_US };
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REG_WRITE(LOAD_LO_REG, dst.lo);
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REG_WRITE(LOAD_HI_REG, dst.hi);
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REG_WRITE(LOAD_REG, 1);
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portEXIT_CRITICAL(&s_time_update_lock);
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}
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void esp_timer_impl_advance(int64_t time_diff_us)
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{
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uint64_t now = esp_timer_impl_get_time();
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esp_timer_impl_set(now + time_diff_us);
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}
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esp_err_t esp_timer_impl_early_init(void)
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{
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PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_LACT, ref_count) {
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if (ref_count == 0) {
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timer_ll_enable_bus_clock(LACT_MODULE, true);
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timer_ll_reset_register(LACT_MODULE);
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}
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}
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REG_WRITE(CONFIG_REG, 0);
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REG_WRITE(LOAD_LO_REG, 0);
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REG_WRITE(LOAD_HI_REG, 0);
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REG_WRITE(ALARM_LO_REG, UINT32_MAX);
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REG_WRITE(ALARM_HI_REG, UINT32_MAX);
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REG_WRITE(LOAD_REG, 1);
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REG_SET_BIT(INT_CLR_REG, TIMG_LACT_INT_CLR);
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REG_SET_FIELD(CONFIG_REG, TIMG_LACT_DIVIDER, APB_CLK_FREQ / 1000000 / TICKS_PER_US);
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REG_SET_BIT(CONFIG_REG, TIMG_LACT_INCREASE |
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TIMG_LACT_LEVEL_INT_EN |
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TIMG_LACT_EN);
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return ESP_OK;
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}
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esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)
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{
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if (s_timer_interrupt_handle[(ISR_HANDLERS == 1) ? 0 : xPortGetCoreID()] != NULL) {
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ESP_EARLY_LOGE(TAG, "timer ISR is already initialized");
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return ESP_ERR_INVALID_STATE;
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}
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int isr_flags = ESP_INTR_FLAG_INTRDISABLED
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| ((1 << CONFIG_ESP_TIMER_INTERRUPT_LEVEL) & ESP_INTR_FLAG_LEVELMASK)
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| ESP_INTR_FLAG_IRAM;
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esp_err_t err = esp_intr_alloc(INTR_SOURCE_LACT, isr_flags,
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&timer_alarm_isr, NULL,
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&s_timer_interrupt_handle[(ISR_HANDLERS == 1) ? 0 : xPortGetCoreID()]);
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if (err != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "Can not allocate ISR handler (0x%0x)", err);
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return err;
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}
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if (s_alarm_handler == NULL) {
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s_alarm_handler = alarm_handler;
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/* In theory, this needs a shared spinlock with the timer group driver.
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* However since esp_timer_impl_init is called early at startup, this
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* will not cause issues in practice.
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*/
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REG_SET_BIT(INT_ENA_REG, TIMG_LACT_INT_ENA);
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esp_timer_impl_update_apb_freq(esp_clk_apb_freq() / 1000000);
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// Set the step for the sleep mode when the timer will work
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// from a slow_clk frequency instead of the APB frequency.
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uint32_t slowclk_ticks_per_us = esp_clk_slowclk_cal_get() * TICKS_PER_US;
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REG_SET_FIELD(RTC_STEP_REG, TIMG_LACT_RTC_STEP_LEN, slowclk_ticks_per_us);
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}
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err = esp_intr_enable(s_timer_interrupt_handle[(ISR_HANDLERS == 1) ? 0 : xPortGetCoreID()]);
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if (err != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "Can not enable ISR (0x%0x)", err);
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}
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return err;
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}
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void esp_timer_impl_deinit(void)
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{
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REG_WRITE(CONFIG_REG, 0);
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REG_SET_BIT(INT_CLR_REG, TIMG_LACT_INT_CLR);
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/* TODO: also clear TIMG_LACT_INT_ENA; however see the note in esp_timer_impl_init. */
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for (unsigned i = 0; i < ISR_HANDLERS; i++) {
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if (s_timer_interrupt_handle[i] != NULL) {
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esp_intr_disable(s_timer_interrupt_handle[i]);
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esp_intr_free(s_timer_interrupt_handle[i]);
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s_timer_interrupt_handle[i] = NULL;
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}
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}
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s_alarm_handler = NULL;
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PERIPH_RCC_RELEASE_ATOMIC(PERIPH_LACT, ref_count) {
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if (ref_count == 0) {
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timer_ll_enable_bus_clock(LACT_MODULE, false);
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}
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}
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}
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uint64_t esp_timer_impl_get_alarm_reg(void)
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{
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portENTER_CRITICAL_SAFE(&s_time_update_lock);
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timer_64b_reg_t alarm = {
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.lo = REG_READ(ALARM_LO_REG),
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.hi = REG_READ(ALARM_HI_REG)
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};
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portEXIT_CRITICAL_SAFE(&s_time_update_lock);
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return alarm.val;
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}
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void esp_timer_private_update_apb_freq(uint32_t apb_ticks_per_us) __attribute__((alias("esp_timer_impl_update_apb_freq")));
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void esp_timer_private_set(uint64_t new_us) __attribute__((alias("esp_timer_impl_set")));
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void esp_timer_private_advance(int64_t time_diff_us) __attribute__((alias("esp_timer_impl_advance")));
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