kopia lustrzana https://github.com/espressif/esp-idf
473 wiersze
16 KiB
C
473 wiersze
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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#include "sdkconfig.h"
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#include <inttypes.h>
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#include "unity.h"
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#include "esp_system.h"
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#include "esp_task_wdt.h"
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#include "esp_attr.h"
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#include "esp_sleep.h"
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#include "soc/rtc.h"
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#include "hal/wdt_hal.h"
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#if CONFIG_IDF_TARGET_ARCH_RISCV
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#include "riscv/rv_utils.h"
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#endif
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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#include "hal/cache_ll.h"
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#endif
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#define RTC_BSS_ATTR __attribute__((section(".rtc.bss")))
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#define CHECK_VALUE 0x89abcdef
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#if CONFIG_SOC_RTC_FAST_MEM_SUPPORTED || CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED
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#define CHECK_RTC_MEM 1
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#endif //CONFIG_SOC_RTC_FAST_MEM_SUPPORTED || CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED
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#if CONFIG_IDF_TARGET_ESP32
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#define DEEPSLEEP "DEEPSLEEP_RESET"
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#define LOAD_STORE_ERROR "LoadStoreError"
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#define RESET "SW_CPU_RESET"
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#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0"
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#define INT_WDT "TG1WDT_SYS_RESET"
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#define RTC_WDT "RTCWDT_RTC_RESET"
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#if CONFIG_ESP32_REV_MIN_FULL >= 300
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#define BROWNOUT "RTCWDT_BROWN_OUT_RESET"
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#else
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#define BROWNOUT "SW_CPU_RESET"
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#endif // CONFIG_ESP32_REV_MIN_FULL >= 300
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#define STORE_ERROR "StoreProhibited"
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#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#define DEEPSLEEP "DSLEEP"
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#define LOAD_STORE_ERROR "LoadStoreError"
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#define RESET "RTC_SW_CPU_RST"
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#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0"
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#define INT_WDT "TG1WDT_SYS_RST"
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#define RTC_WDT "RTCWDT_RTC_RST"
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#define BROWNOUT "BROWN_OUT_RST"
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#define STORE_ERROR "StoreProhibited"
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#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
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#define DEEPSLEEP "DSLEEP"
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#define LOAD_STORE_ERROR "Store access fault"
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#define RESET "RTC_SW_CPU_RST"
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#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0"
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#define INT_WDT "TG1WDT_SYS_RST"
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#define RTC_WDT "RTCWDT_RTC_RST"
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#define BROWNOUT "BROWNOUT_RST"
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#define STORE_ERROR LOAD_STORE_ERROR
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#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT
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#elif CONFIG_IDF_TARGET_ESP32C2
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#define DEEPSLEEP "DSLEEP"
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#define LOAD_STORE_ERROR "Store access fault"
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#define RESET "RTC_SW_CPU_RST"
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#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0"
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#define INT_WDT "TG0WDT_SYS_RST"
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#define RTC_WDT "RTCWDT_RTC_RST"
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#define BROWNOUT "BROWNOUT_RST"
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#define STORE_ERROR LOAD_STORE_ERROR
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#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT
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#elif CONFIG_IDF_TARGET_ESP32C6
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#define DEEPSLEEP "DSLEEP"
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#define LOAD_STORE_ERROR "Store access fault"
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#define RESET "SW_CPU"
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#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0"
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#define INT_WDT "TG1_WDT_HPSYS"
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#define RTC_WDT "LP_WDT_SYS"
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#define BROWNOUT "LP_BOD_SYS"
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#define STORE_ERROR LOAD_STORE_ERROR
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#define INT_WDT_HW_ESP_RST ESP_RST_INT_WDT
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#elif CONFIG_IDF_TARGET_ESP32P4
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#define DEEPSLEEP "DSLEEP"
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#define LOAD_STORE_ERROR "Store access fault"
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#define RESET "SW_CPU_RESET"
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#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0"
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#define INT_WDT "HP_SYS_HP_WDT_RESET"
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#define RTC_WDT "LP_WDT_SYS"
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#define BROWNOUT "LP_BOD_SYS"
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#define STORE_ERROR LOAD_STORE_ERROR
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#define INT_WDT_HW_ESP_RST ESP_RST_WDT // On P4 there is only one reset reason for MWDT0/1
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#endif // CONFIG_IDF_TARGET_ESP32
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/* This test needs special test runners: rev1 silicon, and SPI flash with
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* fast start-up time. Otherwise reset reason will be RTCWDT_RESET.
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*/
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TEST_CASE("reset reason ESP_RST_POWERON", "[reset][ignore]")
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{
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TEST_ASSERT_EQUAL(ESP_RST_POWERON, esp_reset_reason());
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}
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static __NOINIT_ATTR uint32_t s_noinit_val;
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#if CHECK_RTC_MEM
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static RTC_NOINIT_ATTR uint32_t s_rtc_noinit_val;
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static RTC_DATA_ATTR uint32_t s_rtc_data_val;
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static RTC_BSS_ATTR uint32_t s_rtc_bss_val;
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/* There is no practical difference between placing something into RTC_DATA and
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* RTC_RODATA. This only checks a usage pattern where the variable has a non-zero
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* initializer (should be initialized by the bootloader).
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*/
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static RTC_RODATA_ATTR uint32_t s_rtc_rodata_val = CHECK_VALUE;
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static RTC_FAST_ATTR uint32_t s_rtc_force_fast_val;
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static RTC_SLOW_ATTR uint32_t s_rtc_force_slow_val;
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#endif //CHECK_RTC_MEM
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static void setup_values(void)
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{
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s_noinit_val = CHECK_VALUE;
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#if CHECK_RTC_MEM
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s_rtc_noinit_val = CHECK_VALUE;
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s_rtc_data_val = CHECK_VALUE;
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s_rtc_bss_val = CHECK_VALUE;
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TEST_ASSERT_EQUAL_HEX32_MESSAGE(CHECK_VALUE, s_rtc_rodata_val,
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"s_rtc_rodata_val should already be set up");
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s_rtc_force_fast_val = CHECK_VALUE;
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s_rtc_force_slow_val = CHECK_VALUE;
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#endif //CHECK_RTC_MEM
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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/* If internal data is behind a cache it might not be written to the physical memory when we crash
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force a full writeback here to ensure this */
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cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
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#endif
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}
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO IDF-7529
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static void do_deep_sleep(void)
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{
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setup_values();
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esp_sleep_enable_timer_wakeup(10000);
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esp_deep_sleep_start();
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}
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static void check_reset_reason_deep_sleep(void)
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{
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TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
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#if CHECK_RTC_MEM
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_data_val);
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_bss_val);
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_rodata_val);
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_force_fast_val);
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_force_slow_val);
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#endif //CHECK_RTC_MEM
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}
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TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason][reset="DEEPSLEEP"]",
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do_deep_sleep,
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check_reset_reason_deep_sleep);
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#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)
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static void do_exception(void)
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{
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setup_values();
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*(int*)(0x0) = 0;
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}
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static void do_abort(void)
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{
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setup_values();
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abort();
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}
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static void check_reset_reason_panic(void)
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{
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TEST_ASSERT_EQUAL(ESP_RST_PANIC, esp_reset_reason());
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_noinit_val);
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#if CHECK_RTC_MEM
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_data_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_bss_val);
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_rodata_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_fast_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_slow_val);
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#endif //CHECK_RTC_MEM
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}
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TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after exception", "[reset_reason][reset="LOAD_STORE_ERROR","RESET"]",
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do_exception,
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check_reset_reason_panic);
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TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after abort", "[reset_reason][reset=abort,"RESET"]",
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do_abort,
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check_reset_reason_panic);
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static void do_restart(void)
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{
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setup_values();
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esp_restart();
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}
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#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
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static void do_restart_from_app_cpu(void)
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{
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setup_values();
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xTaskCreatePinnedToCore((TaskFunction_t) &do_restart, "restart", 2048, NULL, 5, NULL, 1);
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vTaskDelay(2);
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}
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#endif
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static void check_reset_reason_sw(void)
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{
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TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason());
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_noinit_val);
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#if CHECK_RTC_MEM
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_data_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_bss_val);
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_rodata_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_fast_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_slow_val);
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#endif //CHECK_RTC_MEM
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}
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TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart", "[reset_reason][reset="RESET"]",
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do_restart,
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check_reset_reason_sw);
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#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
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TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart from APP CPU", "[reset_reason][reset="RESET"]",
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do_restart_from_app_cpu,
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check_reset_reason_sw);
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#endif
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static void do_int_wdt(void)
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{
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setup_values();
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#if CONFIG_FREERTOS_SMP
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BaseType_t prev_level = portDISABLE_INTERRUPTS();
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#else
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BaseType_t prev_level = portSET_INTERRUPT_MASK_FROM_ISR();
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#endif
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(void) prev_level;
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while (1);
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}
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static void do_int_wdt_hw(void)
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{
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setup_values();
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#if CONFIG_IDF_TARGET_ARCH_RISCV
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rv_utils_intr_global_disable();
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#else
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XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);
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#endif
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while (1) { }
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}
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static void check_reset_reason_int_wdt_sw(void)
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{
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TEST_ASSERT_EQUAL(ESP_RST_INT_WDT, esp_reset_reason());
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#if CHECK_RTC_MEM
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
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#endif //CHECK_RTC_MEM
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}
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static void check_reset_reason_int_wdt_hw(void)
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{
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TEST_ASSERT_EQUAL(INT_WDT_HW_ESP_RST, esp_reset_reason());
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#if CHECK_RTC_MEM
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
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#endif //CHECK_RTC_MEM
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}
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TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (panic)",
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"[reset_reason][reset="INT_WDT_PANIC","RESET"]",
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do_int_wdt,
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check_reset_reason_int_wdt_sw);
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TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (hw)",
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"[reset_reason][reset="INT_WDT"]",
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do_int_wdt_hw,
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check_reset_reason_int_wdt_hw);
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#if CONFIG_ESP_TASK_WDT_EN
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static void do_task_wdt(void)
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{
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setup_values();
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esp_task_wdt_config_t twdt_config = {
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.timeout_ms = 1000,
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.idle_core_mask = (1 << 0), // Watch core 0 idle
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.trigger_panic = true,
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};
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TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_init(&twdt_config));
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while (1);
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}
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static void check_reset_reason_task_wdt(void)
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{
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TEST_ASSERT_EQUAL(ESP_RST_TASK_WDT, esp_reset_reason());
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_noinit_val);
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#if CHECK_RTC_MEM
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_data_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_bss_val);
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_rodata_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_fast_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_slow_val);
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#endif //CHECK_RTC_MEM
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}
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TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_TASK_WDT after task watchdog",
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"[reset_reason][reset="RESET"]",
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do_task_wdt,
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check_reset_reason_task_wdt);
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#endif // CONFIG_ESP_TASK_WDT_EN
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static void do_rtc_wdt(void)
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{
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setup_values();
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// Enable RTC watchdog for 0.1 second
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wdt_hal_context_t rtc_wdt_ctx;
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
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uint32_t stage_timeout_ticks = rtc_clk_slow_freq_get_hz() / 10;
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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while (1);
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}
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static void check_reset_reason_any_wdt(void)
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{
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TEST_ASSERT_EQUAL(ESP_RST_WDT, esp_reset_reason());
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#if CHECK_RTC_MEM
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
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#endif //CHECK_RTC_MEM
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}
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TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_WDT after RTC watchdog",
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"[reset_reason][reset="RTC_WDT"]",
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do_rtc_wdt,
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check_reset_reason_any_wdt);
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static void do_brownout(void)
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{
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setup_values();
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printf("Manual test: lower the supply voltage to cause brownout\n");
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vTaskSuspend(NULL);
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}
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static void check_reset_reason_brownout(void)
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{
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TEST_ASSERT_EQUAL(ESP_RST_BROWNOUT, esp_reset_reason());
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_noinit_val);
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#if CHECK_RTC_MEM
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_data_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_bss_val);
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TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_rodata_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_fast_val);
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TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_slow_val);
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#endif //CHECK_RTC_MEM
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}
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TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event",
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"[reset_reason][ignore][reset="BROWNOUT"]",
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do_brownout,
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check_reset_reason_brownout);
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#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
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#ifndef CONFIG_FREERTOS_UNICORE
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#if CONFIG_IDF_TARGET_ARCH_XTENSA
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#include "xt_instr_macros.h"
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#include "xtensa/config/specreg.h"
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static int size_stack = 1024 * 3;
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static StackType_t *start_addr_stack;
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static int fibonacci(int n, void* func(void))
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{
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int tmp1 = n, tmp2 = n;
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uint32_t base, start;
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RSR(WINDOWBASE, base);
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RSR(WINDOWSTART, start);
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printf("WINDOWBASE = %-2"PRIi32" WINDOWSTART = 0x%"PRIx32"\n", base, start);
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if (n <= 1) {
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StackType_t *last_addr_stack = esp_cpu_get_sp();
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StackType_t *used_stack = (StackType_t *)(start_addr_stack - last_addr_stack);
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printf("addr_stack = %p, used[%p]/all[0x%x] space in stack\n", last_addr_stack, used_stack, size_stack);
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func();
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return n;
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}
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int fib = fibonacci(n - 1, func) + fibonacci(n - 2, func);
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printf("fib = %d\n", (tmp1 - tmp2) + fib);
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return fib;
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}
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static void test_task(void *func)
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{
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start_addr_stack = esp_cpu_get_sp();
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if (esp_ptr_external_ram(start_addr_stack)) {
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printf("restart_task: uses external stack, addr_stack = %p\n", start_addr_stack);
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} else {
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printf("restart_task: uses internal stack, addr_stack = %p\n", start_addr_stack);
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}
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fibonacci(35, func);
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}
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static void func_do_exception(void)
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{
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*((int *) 0) = 0;
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}
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static void init_restart_task(void)
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{
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StackType_t *stack_for_task = (StackType_t *) heap_caps_calloc(1, size_stack, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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printf("init_task: current addr_stack = %p, stack_for_task = %p\n", esp_cpu_get_sp(), stack_for_task);
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static StaticTask_t task_buf;
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xTaskCreateStaticPinnedToCore(test_task, "test_task", size_stack, esp_restart, 5, stack_for_task, &task_buf, 1);
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while (1) { };
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}
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static void init_task_do_exception(void)
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{
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StackType_t *stack_for_task = (StackType_t *) heap_caps_calloc(1, size_stack, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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printf("init_task: current addr_stack = %p, stack_for_task = %p\n", esp_cpu_get_sp(), stack_for_task);
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static StaticTask_t task_buf;
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xTaskCreateStaticPinnedToCore(test_task, "test_task", size_stack, func_do_exception, 5, stack_for_task, &task_buf, 1);
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|
while (1) { };
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}
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|
|
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static void test1_finish(void)
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|
{
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|
TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason());
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|
printf("test - OK\n");
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|
}
|
|
|
|
static void test2_finish(void)
|
|
{
|
|
TEST_ASSERT_EQUAL(ESP_RST_PANIC, esp_reset_reason());
|
|
printf("test - OK\n");
|
|
}
|
|
|
|
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart in a task with spiram stack", "[spiram_stack][reset="RESET"]",
|
|
init_restart_task,
|
|
test1_finish);
|
|
|
|
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after an exception in a task with spiram stack", "[spiram_stack][reset="STORE_ERROR","RESET"]",
|
|
init_task_do_exception,
|
|
test2_finish);
|
|
|
|
#endif //CONFIG_IDF_TARGET_ARCH_XTENSA
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|
#endif // CONFIG_FREERTOS_UNICORE
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|
#endif // CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
|
|
|
|
/* Not tested here: ESP_RST_SDIO */
|