kopia lustrzana https://github.com/espressif/esp-idf
118 wiersze
3.2 KiB
C
118 wiersze
3.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "soc/soc.h"
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#include "soc/system_reg.h"
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#include "soc/usb_wrap_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Configures the internal PHY for USB_OTG
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*
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* @param hw Start address of the USB Wrap registers
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*/
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static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
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{
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hw->otg_conf.phy_sel = 0;
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}
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/**
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* @brief Configures the external PHY for USB_OTG
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*
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* @param hw Start address of the USB Wrap registers
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*/
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static inline void usb_fsls_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
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{
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//Enable external PHY
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hw->otg_conf.phy_sel = 1;
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}
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/**
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* @brief Configures port loads for the internal PHY
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*
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* @param hw Start address of the USB Wrap registers
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* @param dp_pu D+ pullup load
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* @param dp_pd D+ pulldown load
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* @param dm_pu D- pullup load
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* @param dm_pd D- pulldown load
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*/
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static inline void usb_fsls_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
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{
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usb_wrap_otg_conf_reg_t conf;
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conf.val = hw->otg_conf.val;
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conf.pad_pull_override = 1;
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conf.dp_pullup = dp_pu;
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conf.dp_pulldown = dp_pd;
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conf.dm_pullup = dm_pu;
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conf.dm_pulldown = dm_pd;
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hw->otg_conf.val = conf.val;
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}
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/**
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* @brief Enable the internal PHY control to D+/D- pad
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* @param hw Start address of the USB Wrap registers
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* @param pad_en Enable the PHY control to D+/D- pad
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*/
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static inline void usb_fsls_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
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{
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hw->otg_conf.pad_enable = pad_en;
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}
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/**
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* @brief Enable the internal PHY's test mode
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*
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* @param hw Start address of the USB Wrap registers
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* @param en Whether to enable the internal PHY's test mode
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*/
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static inline void usb_fsls_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
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{
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if (en) {
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// Clear USB_WRAP_TEST_CONF_REG
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hw->test_conf.val = 0;
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// Set USB test pad oen
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hw->test_conf.test_usb_wrap_oe = 1;
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// Enable USB test mode
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hw->test_conf.test_enable = 1;
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} else {
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hw->test_conf.test_enable = 0;
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}
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}
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/**
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* Enable the bus clock for USB Wrap module
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* @param clk_en True if enable the clock of USB Wrap module
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*/
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FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
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{
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REG_SET_FIELD(DPORT_PERIP_CLK_EN0_REG, DPORT_USB_CLK_EN, clk_en);
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}
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// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
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#define usb_fsls_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the USB Wrap module
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*/
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FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_reset_register(void)
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{
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REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 1);
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REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 0);
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}
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// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
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#define usb_fsls_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_reset_register(__VA_ARGS__)
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#ifdef __cplusplus
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}
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#endif
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