kopia lustrzana https://github.com/espressif/esp-idf
211 wiersze
8.7 KiB
C
211 wiersze
8.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "esp_cpu.h"
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#include "esp_fault.h"
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#ifdef BOOTLOADER_BUILD
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// Without L bit set
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#define CONDITIONAL_NONE 0x0
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#define CONDITIONAL_R PMP_R
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#define CONDITIONAL_RX PMP_R | PMP_X
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#define CONDITIONAL_RW PMP_R | PMP_W
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#define CONDITIONAL_RWX PMP_R | PMP_W | PMP_X
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#else
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// With L bit set
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#define CONDITIONAL_NONE NONE
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#define CONDITIONAL_R R
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#define CONDITIONAL_RX RX
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#define CONDITIONAL_RW RW
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#define CONDITIONAL_RWX RWX
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#endif
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#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1))
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#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1))
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static void esp_cpu_configure_invalid_regions(void)
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{
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const unsigned PMA_NONE = PMA_L | PMA_EN;
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__attribute__((unused)) const unsigned PMA_RW = PMA_L | PMA_EN | PMA_R | PMA_W;
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__attribute__((unused)) const unsigned PMA_RX = PMA_L | PMA_EN | PMA_R | PMA_X;
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__attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
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// 1. Gap at bottom of address space
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PMA_ENTRY_SET_TOR(0, SOC_CPU_SUBSYSTEM_LOW, PMA_TOR | PMA_NONE);
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// 2. Gap between CPU subsystem region & IROM
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PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
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// 3. Gap between ROM & RAM
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PMA_ENTRY_SET_TOR(3, SOC_DROM_MASK_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(4, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
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// 4. Gap between DRAM and I_Cache
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PMA_ENTRY_SET_TOR(5, SOC_IRAM_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
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// 5. Gap between D_Cache & LP_RAM
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PMA_ENTRY_SET_TOR(7, SOC_DROM_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(8, SOC_RTC_IRAM_LOW, PMA_TOR | PMA_NONE);
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// 6. Gap between LP memory & peripheral addresses
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PMA_ENTRY_SET_TOR(9, SOC_RTC_IRAM_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(10, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE);
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// 7. End of address space
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PMA_ENTRY_SET_TOR(11, SOC_PERIPHERAL_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(12, UINT32_MAX, PMA_TOR | PMA_NONE);
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}
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void esp_cpu_configure_region_protection(void)
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{
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/* Notes on implementation:
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*
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* 1) Note: ESP32-C6 CPU doesn't support overlapping PMP regions
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*
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* 2) ESP32-C6 supports 16 PMA regions so we use this feature to block all the invalid address ranges
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*
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* 3) We use combination of NAPOT (Naturally Aligned Power Of Two) and TOR (top of range)
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* entries to map all the valid address space, bottom to top. This leaves us with some extra PMP entries
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* which can be used to provide more granular access
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*
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* 4) Entries are grouped in order with some static asserts to try and verify everything is
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* correct.
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*/
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/* There are 4 configuration scenarios for SRAM
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*
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* 1. Bootloader build:
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* - We cannot set the lock bit as we need to reconfigure it again for the application.
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* We configure PMP to cover entire valid IRAM and DRAM range.
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*
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* 2. Application build with CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT enabled
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* - We split the SRAM into IRAM and DRAM such that IRAM region cannot be written to
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* and DRAM region cannot be executed. We use _iram_end and _data_start markers to set the boundaries.
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* We also lock these entries so the R/W/X permissions are enforced even for machine mode
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*
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* 3. Application build with CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT disabled
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* - The IRAM-DRAM split is not enabled so we just need to ensure that access to only valid address ranges are successful
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* so for that we set PMP to cover entire valid IRAM and DRAM region.
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* We also lock these entries so the R/W/X permissions are enforced even for machine mode
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*
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* 4. CPU is in OCD debug mode
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* - The IRAM-DRAM split is not enabled so that OpenOCD can write and execute from IRAM.
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* We set PMP to cover entire valid IRAM and DRAM region.
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* We also lock these entries so the R/W/X permissions are enforced even for machine mode
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*/
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const unsigned NONE = PMP_L;
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__attribute__((unused)) const unsigned R = PMP_L | PMP_R;
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const unsigned RW = PMP_L | PMP_R | PMP_W;
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const unsigned RX = PMP_L | PMP_R | PMP_X;
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const unsigned RWX = PMP_L | PMP_R | PMP_W | PMP_X;
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//
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// Configure all the invalid address regions using PMA
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//
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esp_cpu_configure_invalid_regions();
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//
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// Configure all the valid address regions using PMP
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//
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// 1. CPU Subsystem region - contains debug mode code and interrupt config registers
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const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_CPU_SUBSYSTEM_LOW, SOC_CPU_SUBSYSTEM_HIGH);
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PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX);
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_Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region");
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// 2.1 I/D-ROM
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PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);
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PMP_ENTRY_SET(2, SOC_IROM_MASK_HIGH, PMP_TOR | RX);
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_Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid I/D-ROM region");
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if (esp_cpu_dbgr_is_attached()) {
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// Anti-FI check that cpu is really in ocd mode
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ESP_FAULT_ASSERT(esp_cpu_dbgr_is_attached());
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// 5. IRAM and DRAM
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const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IRAM_LOW, SOC_IRAM_HIGH);
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PMP_ENTRY_SET(5, pmpaddr5, PMP_NAPOT | RWX);
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_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
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} else {
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#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
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extern int _iram_end;
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// 5. IRAM and DRAM
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/* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
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* Bootloader might have given extra permissions and those won't be cleared
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*/
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PMP_ENTRY_CFG_RESET(5);
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PMP_ENTRY_CFG_RESET(6);
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PMP_ENTRY_CFG_RESET(7);
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PMP_ENTRY_SET(5, SOC_IRAM_LOW, NONE);
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PMP_ENTRY_SET(6, (int)&_iram_end, PMP_TOR | RX);
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PMP_ENTRY_SET(7, SOC_DRAM_HIGH, PMP_TOR | RW);
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#else
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// 5. IRAM and DRAM
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const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IRAM_LOW, SOC_IRAM_HIGH);
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PMP_ENTRY_SET(5, pmpaddr5, PMP_NAPOT | CONDITIONAL_RWX);
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_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
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#endif
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}
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#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
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extern int _instruction_reserved_end;
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extern int _rodata_reserved_end;
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const uint32_t irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
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const uint32_t drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
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// 4. I_Cache / D_Cache (flash)
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PMP_ENTRY_CFG_RESET(8);
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PMP_ENTRY_CFG_RESET(9);
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PMP_ENTRY_CFG_RESET(10);
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PMP_ENTRY_SET(8, SOC_IROM_LOW, NONE);
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PMP_ENTRY_SET(9, irom_resv_end, PMP_TOR | RX);
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PMP_ENTRY_SET(10, drom_resv_end, PMP_TOR | R);
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#else
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// 4. I_Cache / D_Cache (flash)
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const uint32_t pmpaddr8 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
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PMP_ENTRY_SET(8, pmpaddr8, PMP_NAPOT | CONDITIONAL_RX);
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_Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I/D_Cache region");
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#endif
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// 6. LP memory
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#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
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extern int _rtc_text_end;
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/* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
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* Bootloader might have given extra permissions and those won't be cleared
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*/
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PMP_ENTRY_CFG_RESET(11);
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PMP_ENTRY_CFG_RESET(12);
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PMP_ENTRY_CFG_RESET(13);
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PMP_ENTRY_CFG_RESET(14);
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PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW, NONE);
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#if CONFIG_ULP_COPROC_RESERVE_MEM
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// First part of LP mem is reserved for coprocessor
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PMP_ENTRY_SET(12, SOC_RTC_IRAM_LOW + CONFIG_ULP_COPROC_RESERVE_MEM, PMP_TOR | RW);
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#else // CONFIG_ULP_COPROC_RESERVE_MEM
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// Repeat same previous entry, to ensure next entry has correct base address (TOR)
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PMP_ENTRY_SET(12, SOC_RTC_IRAM_LOW, NONE);
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#endif // !CONFIG_ULP_COPROC_RESERVE_MEM
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PMP_ENTRY_SET(13, (int)&_rtc_text_end, PMP_TOR | RX);
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PMP_ENTRY_SET(14, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
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#else
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const uint32_t pmpaddr11 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
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PMP_ENTRY_SET(11, pmpaddr11, PMP_NAPOT | CONDITIONAL_RWX);
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_Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
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#endif
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// 7. Peripheral addresses
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const uint32_t pmpaddr15 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
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PMP_ENTRY_SET(15, pmpaddr15, PMP_NAPOT | RW);
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_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
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}
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