kopia lustrzana https://github.com/espressif/esp-idf
536 wiersze
27 KiB
C
536 wiersze
27 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* These defines are parsed and imported as kconfig variables via the script
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* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
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*
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* If this file is changed the script will automatically run the script
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* and generate the kconfig variables as part of the pre-commit hooks.
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*
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* It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md`
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*/
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#pragma once
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_ADC_SUPPORTED 1
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#define SOC_ANA_CMPR_SUPPORTED 1
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#define SOC_DEDICATED_GPIO_SUPPORTED 1
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#define SOC_UART_SUPPORTED 1
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#define SOC_GDMA_SUPPORTED 1
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#define SOC_AHB_GDMA_SUPPORTED 1
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#define SOC_ASYNC_MEMCPY_SUPPORTED 1
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#define SOC_PCNT_SUPPORTED 1
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#define SOC_MCPWM_SUPPORTED 1
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#define SOC_TWAI_SUPPORTED 1
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#define SOC_BT_SUPPORTED 1
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#define SOC_GPTIMER_SUPPORTED 1
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#define SOC_IEEE802154_SUPPORTED 1
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#define SOC_IEEE802154_BLE_ONLY 1
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#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
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#define SOC_TEMP_SENSOR_SUPPORTED 1
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#define SOC_SUPPORTS_SECURE_DL_MODE 1
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#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
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#define SOC_EFUSE_SUPPORTED 1
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#define SOC_RTC_FAST_MEM_SUPPORTED 1
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#define SOC_RTC_MEM_SUPPORTED 1
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#define SOC_I2S_SUPPORTED 1
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#define SOC_SDM_SUPPORTED 1
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#define SOC_ETM_SUPPORTED 1
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#define SOC_RMT_SUPPORTED 1
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#define SOC_PARLIO_SUPPORTED 1
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#define SOC_GPSPI_SUPPORTED 1
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#define SOC_LEDC_SUPPORTED 1
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#define SOC_I2C_SUPPORTED 1
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#define SOC_SYSTIMER_SUPPORTED 1
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#define SOC_SUPPORT_COEXISTENCE 1
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#define SOC_AES_SUPPORTED 1
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#define SOC_MPI_SUPPORTED 1
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#define SOC_SHA_SUPPORTED 1
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#define SOC_HMAC_SUPPORTED 1
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#define SOC_DIG_SIGN_SUPPORTED 1
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#define SOC_ECC_SUPPORTED 1
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#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1
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#define SOC_ECDSA_SUPPORTED 1
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#define SOC_FLASH_ENC_SUPPORTED 1
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#define SOC_SECURE_BOOT_SUPPORTED 1
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#define SOC_BOD_SUPPORTED 1
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#define SOC_APM_SUPPORTED 1
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#define SOC_PMU_SUPPORTED 1
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#define SOC_LP_TIMER_SUPPORTED 1
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#define SOC_LP_AON_SUPPORTED 1
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#define SOC_PAU_SUPPORTED 1
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#define SOC_CLK_TREE_SUPPORTED 1
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#define SOC_ASSIST_DEBUG_SUPPORTED 1
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#define SOC_WDT_SUPPORTED 1
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#define SOC_SPI_FLASH_SUPPORTED 1
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#define SOC_RNG_SUPPORTED 1
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#define SOC_LIGHT_SLEEP_SUPPORTED 1
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#define SOC_DEEP_SLEEP_SUPPORTED 1
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/*-------------------------- XTAL CAPS ---------------------------------------*/
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#define SOC_XTAL_SUPPORT_32M 1
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/*-------------------------- AES CAPS -----------------------------------------*/
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#define SOC_AES_SUPPORT_DMA (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_AES_GDMA (1)
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#define SOC_AES_SUPPORT_AES_128 (1)
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#define SOC_AES_SUPPORT_AES_256 (1)
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/*-------------------------- ADC CAPS -------------------------------*/
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/*!< SAR ADC Module*/
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#define SOC_ADC_DIG_CTRL_SUPPORTED 1
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#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
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#define SOC_ADC_MONITOR_SUPPORTED 1
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#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
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#define SOC_ADC_DMA_SUPPORTED 1
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#define SOC_ADC_PERIPH_NUM (1U)
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#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5)
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#define SOC_ADC_MAX_CHANNEL_NUM (5)
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#define SOC_ADC_ATTEN_NUM (4)
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/*!< Digital */
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#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
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#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
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#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
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#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
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#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
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#define SOC_ADC_DIGI_MONITOR_NUM (2)
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#define SOC_ADC_DIGI_RESULT_BYTES (4)
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#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
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/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */
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#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
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#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
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/*!< RTC */
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#define SOC_ADC_RTC_MIN_BITWIDTH (12)
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#define SOC_ADC_RTC_MAX_BITWIDTH (12)
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/*!< Calibration */
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#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
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#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
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#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
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/*!< Interrupt */
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#define SOC_ADC_TEMPERATURE_SHARE_INTR (1)
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/*!< ADC power control is shared by PWDET */
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#define SOC_ADC_SHARED_POWER 1
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// ESP32H2-TODO: Copy from esp32c6, need check
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/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
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#define SOC_APB_BACKUP_DMA (0)
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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/*-------------------------- CACHE CAPS --------------------------------------*/
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#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
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#define SOC_CACHE_FREEZE_SUPPORTED 1
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/*-------------------------- CPU CAPS ----------------------------------------*/
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#define SOC_CPU_CORES_NUM (1U)
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#define SOC_CPU_INTR_NUM 32
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#define SOC_CPU_HAS_FLEXIBLE_INTC 1
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#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller
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#define SOC_CPU_BREAKPOINTS_NUM 4
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#define SOC_CPU_WATCHPOINTS_NUM 4
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#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
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#define SOC_CPU_HAS_PMA 1
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#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1
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/*-------------------------- MMU CAPS ----------------------------------------*/
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#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1)
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#define SOC_MMU_PERIPH_NUM (1U)
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#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U)
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#define SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */
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/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
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/** The maximum length of a Digital Signature in bits. */
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#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
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/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
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#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
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/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
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See TRM DS chapter for more details */
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#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
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/*-------------------------- GDMA CAPS -------------------------------------*/
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#define SOC_AHB_GDMA_VERSION 1U
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#define SOC_GDMA_NUM_GROUPS_MAX 1U
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#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
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#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
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#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
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/*-------------------------- ETM CAPS --------------------------------------*/
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#define SOC_ETM_GROUPS 1U // Number of ETM groups
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#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
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/*-------------------------- GPIO CAPS ---------------------------------------*/
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// ESP32-H2 has 1 GPIO peripheral
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#define SOC_GPIO_PORT 1U
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#define SOC_GPIO_PIN_COUNT 28
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#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
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#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
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#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
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#define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse
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// GPIO peripheral has the ETM extension
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#define SOC_GPIO_SUPPORT_ETM 1
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#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
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#define SOC_GPIO_ETM_TASKS_PER_GROUP 8
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// Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins)
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// Digital IOs have their own registers to control pullup/down/capability
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// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers
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#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
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// GPIO7~14 on ESP32H2 can support chip deep sleep wakeup through EXT1 wake up
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#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1)
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#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
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#define SOC_GPIO_IN_RANGE_MAX 27
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#define SOC_GPIO_OUT_RANGE_MAX 27
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// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27)
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#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL
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// Support to force hold all IOs
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#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
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// Support to hold a single digital I/O when the digital domain is powered off
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#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
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// The Clock Out singnal is route to the pin by GPIO matrix
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#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
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#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
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/*-------------------------- RTCIO CAPS --------------------------------------*/
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/* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported
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* for hold, wake & 32kHz crystal functions - via LP_AON registers */
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#define SOC_RTCIO_PIN_COUNT (8U)
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#define SOC_RTCIO_HOLD_SUPPORTED (1)
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#define SOC_RTCIO_VALID_RTCIO_MASK (0x7F80)
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/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
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#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
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#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
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#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
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/*------------------------- Analog Comparator CAPS ---------------------------*/
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#define SOC_ANA_CMPR_NUM (1U)
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#define SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO (1)
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/*-------------------------- I2C CAPS ----------------------------------------*/
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// ESP32-H2 has 2 I2C
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#define SOC_I2C_NUM (2U)
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
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#define SOC_I2C_SUPPORT_SLAVE (1)
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#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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#define SOC_I2C_SUPPORT_XTAL (1)
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#define SOC_I2C_SUPPORT_RTC (1)
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#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
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#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
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#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
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#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
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#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
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/*-------------------------- I2S CAPS ----------------------------------------*/
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#define SOC_I2S_NUM (1U)
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#define SOC_I2S_HW_VERSION_2 (1)
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#define SOC_I2S_SUPPORTS_XTAL (1)
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#define SOC_I2S_SUPPORTS_PLL_F96M (1)
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#define SOC_I2S_SUPPORTS_PLL_F64M (1)
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#define SOC_I2S_SUPPORTS_PCM (1)
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#define SOC_I2S_SUPPORTS_PDM (1)
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#define SOC_I2S_SUPPORTS_PDM_TX (1)
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#define SOC_I2S_PDM_MAX_TX_LINES (2)
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#define SOC_I2S_SUPPORTS_TDM (1)
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#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
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/*-------------------------- LEDC CAPS ---------------------------------------*/
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#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
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#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
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#define SOC_LEDC_CHANNEL_NUM (6)
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#define SOC_LEDC_TIMER_BIT_WIDTH (20)
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#define SOC_LEDC_SUPPORT_FADE_STOP (1)
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#define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
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#define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
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#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
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/*-------------------------- MPU CAPS ----------------------------------------*/
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#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
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#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
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#define SOC_MPU_REGIONS_MAX_NUM 8
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#define SOC_MPU_REGION_RO_SUPPORTED 0
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#define SOC_MPU_REGION_WO_SUPPORTED 0
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/*-------------------------- PCNT CAPS ---------------------------------------*/
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#define SOC_PCNT_GROUPS 1U
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#define SOC_PCNT_UNITS_PER_GROUP 4
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#define SOC_PCNT_CHANNELS_PER_UNIT 2
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#define SOC_PCNT_THRES_POINT_PER_UNIT 2
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#define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
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/*--------------------------- RMT CAPS ---------------------------------------*/
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#define SOC_RMT_GROUPS 1U /*!< One RMT group */
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#define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */
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#define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */
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#define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */
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#define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
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#define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */
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#define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */
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#define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */
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#define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
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#define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */
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#define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */
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#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */
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#define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
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#define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
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/*-------------------------- MCPWM CAPS --------------------------------------*/
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#define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
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#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
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#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
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#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
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#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
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#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
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#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
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#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
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#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
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#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
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#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
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#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
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#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
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/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
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// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
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/*-------------------------- PARLIO CAPS --------------------------------------*/
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#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
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#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
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#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
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#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
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#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
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#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
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#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
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#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
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#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
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/*--------------------------- MPI CAPS ---------------------------------------*/
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#define SOC_MPI_MEM_BLOCKS_NUM (4)
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#define SOC_MPI_OPERATIONS_NUM (3)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (3072)
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* The SHA engine is able to resume hashing from a user */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_SHA_GDMA (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
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#define SOC_SDM_GROUPS 1U
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#define SOC_SDM_CHANNELS_PER_GROUP 4
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#define SOC_SDM_CLK_SUPPORT_PLL_F48M 1
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#define SOC_SDM_CLK_SUPPORT_XTAL 1
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 2
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#define SOC_SPI_PERIPH_CS_NUM(i) 6
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#define SOC_SPI_MAX_CS_NUM 6
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#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
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#define SOC_SPI_SUPPORT_DDRCLK 1
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#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
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#define SOC_SPI_SUPPORT_CD_SIG 1
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#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
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#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
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#define SOC_SPI_SUPPORT_CLK_XTAL 1
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#define SOC_SPI_SUPPORT_CLK_PLL_F48M 1
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#define SOC_SPI_SUPPORT_CLK_RC_FAST 1
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
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#define SOC_MEMSPI_IS_INDEPENDENT 1
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#define SOC_SPI_MAX_PRE_DIVIDER 16
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/*-------------------------- SPI MEM CAPS ---------------------------------------*/
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#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
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#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
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#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
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#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
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#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
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#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
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#define SOC_SPI_MEM_SUPPORT_WRAP (1)
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#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1
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#define SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT 1
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
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#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
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#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part
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#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part
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#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed to 2 when clock source is XTAL
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#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
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#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
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#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
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#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
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/*-------------------------- LP_TIMER CAPS ----------------------------------*/
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#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
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#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
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/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
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#define SOC_TIMER_GROUPS (2)
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#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
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#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
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#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
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#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
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#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
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#define SOC_TIMER_SUPPORT_ETM (1)
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/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
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#define SOC_MWDT_SUPPORT_XTAL (1)
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/*-------------------------- TWAI CAPS ---------------------------------------*/
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#define SOC_TWAI_CONTROLLER_NUM 1UL
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#define SOC_TWAI_CLK_SUPPORT_XTAL 1
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#define SOC_TWAI_BRP_MIN 2
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#define SOC_TWAI_BRP_MAX 32768
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#define SOC_TWAI_SUPPORTS_RX_STATUS 1
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/*-------------------------- eFuse CAPS----------------------------*/
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#define SOC_EFUSE_DIS_PAD_JTAG 1
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#define SOC_EFUSE_DIS_USB_JTAG 1
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#define SOC_EFUSE_DIS_DIRECT_BOOT 1
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#define SOC_EFUSE_SOFT_DIS_JTAG 1
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#define SOC_EFUSE_DIS_ICACHE 1
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#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES and ECDSA key purposes not supported for this block
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#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA
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/*-------------------------- Secure Boot CAPS----------------------------*/
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#define SOC_SECURE_BOOT_V2_RSA 1
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#define SOC_SECURE_BOOT_V2_ECC 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
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#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
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#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
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/*-------------------------- Flash Encryption CAPS----------------------------*/
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#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
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#define SOC_FLASH_ENCRYPTION_XTS_AES 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
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/*------------------------ Anti DPA (Security) CAPS --------------------------*/
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#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
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/*-------------------------- UART CAPS ---------------------------------------*/
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// ESP32-H2 has 2 UARTs
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#define SOC_UART_NUM (2)
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#define SOC_UART_HP_NUM (2)
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
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#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
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#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
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// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
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#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
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// TODO: IDF-5679 (Copy from esp32c6, need check)
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/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
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#define SOC_COEX_HW_PTI (1)
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/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
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#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
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#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
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// TODO: IDF-6337
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/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
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#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
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/*-------------------------- Power Management CAPS ----------------------------*/
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#define SOC_PM_SUPPORT_BT_WAKEUP (1)
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#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
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#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configue the EXT1 trigger level */
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#define SOC_PM_SUPPORT_CPU_PD (1)
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#define SOC_PM_SUPPORT_MODEM_PD (1) /*!<modem includes BLE and 15.4 */
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#define SOC_PM_SUPPORT_XTAL32K_PD (1)
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#define SOC_PM_SUPPORT_RC32K_PD (1)
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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#define SOC_PM_SUPPORT_TOP_PD (1)
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#define SOC_PM_PAU_LINK_NUM (4)
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#define SOC_PM_CPU_RETENTION_BY_SW (1)
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#define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
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#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
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#define SOC_PM_RETENTION_SW_TRIGGER_REGDMA (1) /*!< In esp32H2, regdma will power off when entering sleep */
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
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#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
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#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
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#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */
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#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL (1) /*!< Support LP_PLL clock as the LP_FAST clock source */
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#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
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#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
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/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
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#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
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#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
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#define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1)
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#define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM (1)
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/*--------------------------------- RNG CAPS --------------------------------------------*/
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#define SOC_RNG_CLOCK_IS_INDEPENDENT (1)
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/*---------------------------------- Bluetooth CAPS ----------------------------------*/
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#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */
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#define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */
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#define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */
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#define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
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#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
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#define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */
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#define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */
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#define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */
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