kopia lustrzana https://github.com/espressif/esp-idf
634 wiersze
28 KiB
Plaintext
634 wiersze
28 KiB
Plaintext
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menu "ESP System Settings"
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# Insert chip-specific cpu config
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rsource "./port/soc/$IDF_TARGET/Kconfig.cpu"
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orsource "./port/soc/$IDF_TARGET/Kconfig.cache"
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orsource "./port/soc/$IDF_TARGET/Kconfig.memory"
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orsource "./port/soc/$IDF_TARGET/Kconfig.tracemem"
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choice ESP_SYSTEM_PANIC
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prompt "Panic handler behaviour"
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default ESP_SYSTEM_PANIC_PRINT_REBOOT
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help
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If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
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invoked. Configure the panic handler's action here.
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config ESP_SYSTEM_PANIC_PRINT_HALT
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bool "Print registers and halt"
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depends on !ESP_SYSTEM_GDBSTUB_RUNTIME
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help
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Outputs the relevant registers over the serial port and halt the
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processor. Needs a manual reset to restart.
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config ESP_SYSTEM_PANIC_PRINT_REBOOT
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bool "Print registers and reboot"
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depends on !ESP_SYSTEM_GDBSTUB_RUNTIME
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help
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Outputs the relevant registers over the serial port and immediately
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reset the processor.
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config ESP_SYSTEM_PANIC_SILENT_REBOOT
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bool "Silent reboot"
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depends on !ESP_SYSTEM_GDBSTUB_RUNTIME
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help
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Just resets the processor without outputting anything
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config ESP_SYSTEM_PANIC_GDBSTUB
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bool "GDBStub on panic"
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depends on ESP_GDBSTUB_ENABLED
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help
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Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
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of the crash.
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endchoice
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config ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS
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int "Panic reboot delay (Seconds)"
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default 0
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range 0 99
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depends on ESP_SYSTEM_PANIC_PRINT_REBOOT
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help
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After the panic handler executes, you can specify a number of seconds to
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wait before the device reboots.
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config ESP_SYSTEM_SINGLE_CORE_MODE
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bool
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default n
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help
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Only initialize and use the main core.
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config ESP_SYSTEM_RTC_EXT_XTAL
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# This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
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# e.g. It will be selected on when RTC_CLK_SRC_EXT_CRYS is on
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bool
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default n
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config ESP_SYSTEM_RTC_EXT_OSC
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# This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
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# e.g. It will be selected on when ESPX_RTC_CLK_SRC_EXT_OSC is on
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bool
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default n
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config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES
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int "Bootstrap cycles for external 32kHz crystal"
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depends on ESP_SYSTEM_RTC_EXT_XTAL
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default 5 if IDF_TARGET_ESP32
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default 0
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range 0 32768
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help
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To reduce the startup time of an external RTC crystal,
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we bootstrap it with a 32kHz square wave for a fixed number of cycles.
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Setting 0 will disable bootstrapping (if disabled, the crystal may take
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longer to start up or fail to oscillate under some conditions).
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If this value is too high, a faulty crystal may initially start and then fail.
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If this value is too low, an otherwise good crystal may not start.
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To accurately determine if the crystal has started,
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set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000).
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config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
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bool
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default y if IDF_TARGET_ESP32 && ESP_SYSTEM_SINGLE_CORE_MODE
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default y if IDF_TARGET_ESP32S2
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default y if IDF_TARGET_ESP32C3
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default y if IDF_TARGET_ESP32S3
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default y if IDF_TARGET_ESP32C6
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default n if IDF_TARGET_ESP32H2 # IDF-5667
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default y if IDF_TARGET_ESP32P4
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depends on SOC_RTC_FAST_MEM_SUPPORTED
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config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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bool "Enable RTC fast memory for dynamic allocations"
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default y
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depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
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help
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This config option allows to add RTC fast memory region to system heap with capability
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similar to that of DRAM region but without DMA. This memory will be consumed first per
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heap initialization order by early startup services and scheduler related code. Speed
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wise RTC fast memory operates on APB clock and hence does not have much performance impact.
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config ESP_SYSTEM_USE_EH_FRAME
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bool "Generate and use eh_frame for backtracing"
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default n
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depends on IDF_TARGET_ARCH_RISCV
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help
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Generate DWARF information for each function of the project. These information will parsed and used to
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perform backtracing when panics occur. Activating this option will activate asynchronous frame unwinding
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and generation of both .eh_frame and .eh_frame_hdr sections, resulting in a bigger binary size (20% to
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100% larger). The main purpose of this option is to be able to have a backtrace parsed and printed by
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the program itself, regardless of the serial monitor used.
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This option shall NOT be used for production.
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menu "Memory protection"
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config ESP_SYSTEM_PMP_IDRAM_SPLIT
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bool "Enable IRAM/DRAM split protection"
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depends on SOC_CPU_IDRAM_SPLIT_USING_PMP
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default "y"
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help
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If enabled, the CPU watches all the memory access and raises an exception in case
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of any memory violation. This feature automatically splits
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the SRAM memory, using PMP, into data and instruction segments and sets Read/Execute permissions
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for the instruction part (below given splitting address) and Read/Write permissions
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for the data part (above the splitting address). The memory protection is effective
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on all access through the IRAM0 and DRAM0 buses.
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config ESP_SYSTEM_MEMPROT_FEATURE
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bool "Enable memory protection"
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depends on SOC_MEMPROT_SUPPORTED
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default "y"
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help
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If enabled, the permission control module watches all the memory access and fires the panic handler
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if a permission violation is detected. This feature automatically splits
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the SRAM memory into data and instruction segments and sets Read/Execute permissions
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for the instruction part (below given splitting address) and Read/Write permissions
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for the data part (above the splitting address). The memory protection is effective
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on all access through the IRAM0 and DRAM0 buses.
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config ESP_SYSTEM_MEMPROT_FEATURE_LOCK
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depends on ESP_SYSTEM_MEMPROT_FEATURE
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bool "Lock memory protection settings"
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default "y"
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help
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Once locked, memory protection settings cannot be changed anymore.
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The lock is reset only on the chip startup.
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endmenu # Memory protection
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config ESP_SYSTEM_EVENT_QUEUE_SIZE
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int "System event queue size"
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default 32
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help
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Config system event queue size in different application.
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config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
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int "Event loop task stack size"
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default 2304
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help
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Config system event task stack size in different application.
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config ESP_MAIN_TASK_STACK_SIZE
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int "Main task stack size"
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default 3584
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help
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Configure the "main task" stack size. This is the stack of the task
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which calls app_main(). If app_main() returns then this task is deleted
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and its stack memory is freed.
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choice ESP_MAIN_TASK_AFFINITY
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prompt "Main task core affinity"
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default ESP_MAIN_TASK_AFFINITY_CPU0
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help
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Configure the "main task" core affinity. This is the used core of the task
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which calls app_main(). If app_main() returns then this task is deleted.
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config ESP_MAIN_TASK_AFFINITY_CPU0
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bool "CPU0"
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config ESP_MAIN_TASK_AFFINITY_CPU1
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bool "CPU1"
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depends on !FREERTOS_UNICORE
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config ESP_MAIN_TASK_AFFINITY_NO_AFFINITY
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bool "No affinity"
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endchoice
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config ESP_MAIN_TASK_AFFINITY
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hex
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default 0x0 if ESP_MAIN_TASK_AFFINITY_CPU0
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default 0x1 if ESP_MAIN_TASK_AFFINITY_CPU1
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default FREERTOS_NO_AFFINITY if ESP_MAIN_TASK_AFFINITY_NO_AFFINITY
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config ESP_MINIMAL_SHARED_STACK_SIZE
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int "Minimal allowed size for shared stack"
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default 2048
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help
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Minimal value of size, in bytes, accepted to execute a expression
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with shared stack.
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choice ESP_CONSOLE_UART
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prompt "Channel for console output"
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default ESP_CONSOLE_UART_DEFAULT
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help
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Select where to send console output (through stdout and stderr).
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- Default is to use UART0 on pre-defined GPIOs.
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- If "Custom" is selected, UART0 or UART1 can be chosen,
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and any pins can be selected.
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- If "None" is selected, there will be no console output on any UART, except
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for initial output from ROM bootloader. This ROM output can be suppressed by
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GPIO strapping or EFUSE, refer to chip datasheet for details.
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- On chips with USB OTG peripheral, "USB CDC" option redirects output to the
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CDC port. This option uses the CDC driver in the chip ROM.
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This option is incompatible with TinyUSB stack.
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- On chips with an USB serial/JTAG debug controller, selecting the option
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for that redirects output to the CDC/ACM (serial port emulation) component
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of that device.
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config ESP_CONSOLE_UART_DEFAULT
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bool "Default: UART0"
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config ESP_CONSOLE_USB_CDC
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bool "USB CDC"
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# && !TINY_USB is because the ROM CDC driver is currently incompatible with TinyUSB.
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depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !TINY_USB
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config ESP_CONSOLE_USB_SERIAL_JTAG
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bool "USB Serial/JTAG Controller"
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select ESPTOOLPY_NO_STUB if IDF_TARGET_ESP32C3 #ESPTOOL-252
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depends on SOC_USB_SERIAL_JTAG_SUPPORTED
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config ESP_CONSOLE_UART_CUSTOM
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bool "Custom UART"
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config ESP_CONSOLE_NONE
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bool "None"
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endchoice
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choice ESP_CONSOLE_SECONDARY
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depends on SOC_USB_SERIAL_JTAG_SUPPORTED
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prompt "Channel for console secondary output"
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default ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
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help
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This secondary option supports output through other specific port like USB_SERIAL_JTAG
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when UART0 port as a primary is selected but not connected. This secondary output currently only supports
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non-blocking mode without using REPL. If you want to output in blocking mode with REPL or
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input through this secondary port, please change the primary config to this port
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in `Channel for console output` menu.
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config ESP_CONSOLE_SECONDARY_NONE
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bool "No secondary console"
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config ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
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bool "USB_SERIAL_JTAG PORT"
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depends on !ESP_CONSOLE_USB_SERIAL_JTAG
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help
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This option supports output through USB_SERIAL_JTAG port when the UART0 port is not connected.
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The output currently only supports non-blocking mode without using the console.
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If you want to output in blocking mode with REPL or input through USB_SERIAL_JTAG port,
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please change the primary config to ESP_CONSOLE_USB_SERIAL_JTAG above.
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endchoice
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config ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
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# Internal option, indicates that console USB SERIAL JTAG is used
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bool
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default y if ESP_CONSOLE_USB_SERIAL_JTAG || ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
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select USJ_ENABLE_USB_SERIAL_JTAG
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config ESP_CONSOLE_UART
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# Internal option, indicates that console UART is used (and not USB, for example)
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bool
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default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM
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choice ESP_CONSOLE_UART_NUM
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prompt "UART peripheral to use for console output (0-1)"
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depends on ESP_CONSOLE_UART_CUSTOM
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default ESP_CONSOLE_UART_CUSTOM_NUM_0
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help
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This UART peripheral is used for console output from the ESP-IDF Bootloader and the app.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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Due to an ESP32 ROM bug, UART2 is not supported for console output
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via esp_rom_printf.
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config ESP_CONSOLE_UART_CUSTOM_NUM_0
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bool "UART0"
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config ESP_CONSOLE_UART_CUSTOM_NUM_1
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bool "UART1"
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endchoice
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config ESP_CONSOLE_UART_NUM
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int
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default 0 if ESP_CONSOLE_UART_DEFAULT
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default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
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default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
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default -1 if !ESP_CONSOLE_UART
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config ESP_CONSOLE_ROM_SERIAL_PORT_NUM
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# This config is used for the correct serial number used in ROM uart function.
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int
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default 0 if ESP_CONSOLE_UART_DEFAULT
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default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
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default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
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# Can be extended if we have more uarts.
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default ESP_ROM_USB_SERIAL_DEVICE_NUM if ESP_CONSOLE_USB_SERIAL_JTAG
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default ESP_ROM_USB_OTG_NUM if ESP_CONSOLE_USB_CDC
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default -1 if ESP_CONSOLE_NONE
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config ESP_CONSOLE_UART_TX_GPIO
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int "UART TX on GPIO#"
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depends on ESP_CONSOLE_UART_CUSTOM
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range 0 SOC_GPIO_OUT_RANGE_MAX
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default 1 if IDF_TARGET_ESP32
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default 20 if IDF_TARGET_ESP32C2
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default 21 if IDF_TARGET_ESP32C3
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default 10 if IDF_TARGET_ESP32C5
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default 16 if IDF_TARGET_ESP32C6
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default 37 if IDF_TARGET_ESP32P4
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default 24 if IDF_TARGET_ESP32H2
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default 43
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help
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This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including
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boot log output and default standard output and standard error of the app).
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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config ESP_CONSOLE_UART_RX_GPIO
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int "UART RX on GPIO#"
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depends on ESP_CONSOLE_UART_CUSTOM
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range 0 SOC_GPIO_IN_RANGE_MAX
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default 3 if IDF_TARGET_ESP32
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default 19 if IDF_TARGET_ESP32C2
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default 20 if IDF_TARGET_ESP32C3
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default 11 if IDF_TARGET_ESP32C5
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default 17 if IDF_TARGET_ESP32C6
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default 38 if IDF_TARGET_ESP32P4
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default 23 if IDF_TARGET_ESP32H2
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default 44
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help
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This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including
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default default standard input of the app).
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Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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config ESP_CONSOLE_UART_BAUDRATE
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int
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prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM
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depends on ESP_CONSOLE_UART
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default 74880 if (IDF_TARGET_ESP32C2 && XTAL_FREQ_26)
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default 138240 if (IDF_TARGET_ESP32C5_BETA3_VERSION && XTAL_FREQ_48)
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default 115200
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range 1200 4000000 if !PM_ENABLE
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range 1200 1000000 if PM_ENABLE
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help
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This baud rate is used by both the ESP-IDF Bootloader and the app (including
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boot log output and default standard input/output/error of the app).
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The app's maximum baud rate depends on the UART clock source. If Power Management is disabled,
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the UART clock source is the APB clock and all baud rates in the available range will be sufficiently
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accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided
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from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be
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accurate.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE
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int "Size of USB CDC RX buffer"
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depends on ESP_CONSOLE_USB_CDC
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default 64
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range 4 16384
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help
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Set the size of USB CDC RX buffer. Increase the buffer size if your application
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is often receiving data over USB CDC.
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config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
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bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC"
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depends on ESP_CONSOLE_USB_CDC
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default n
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help
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If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC.
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Disabling this option saves about 1kB or RAM.
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config ESP_INT_WDT
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bool "Interrupt watchdog"
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default y
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help
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This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
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either because a task turned off interrupts and did not turn them on for a long time, or because an
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interrupt handler did not return. It will try to invoke the panic handler first and failing that
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reset the SoC.
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config ESP_INT_WDT_TIMEOUT_MS
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int "Interrupt watchdog timeout (ms)"
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depends on ESP_INT_WDT
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default 300 if !(SPIRAM && IDF_TARGET_ESP32)
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default 800 if (SPIRAM && IDF_TARGET_ESP32)
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range 10 10000
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help
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The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
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config ESP_INT_WDT_CHECK_CPU1
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bool "Also watch CPU1 tick interrupt"
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depends on ESP_INT_WDT && !FREERTOS_UNICORE
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default y
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help
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Also detect if interrupts on CPU 1 are disabled for too long.
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config ESP_TASK_WDT_EN
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bool "Enable Task Watchdog Timer"
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default y
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help
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The Task Watchdog Timer can be used to make sure individual tasks are still
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running. Enabling this option will enable the Task Watchdog Timer. It can be
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either initialized automatically at startup or initialized after startup
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(see Task Watchdog Timer API Reference)
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config ESP_TASK_WDT_USE_ESP_TIMER
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# Software implementation of Task Watchdog, handy for targets with only a single
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# Timer Group, such as the ESP32-C2
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bool
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depends on ESP_TASK_WDT_EN
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default y if IDF_TARGET_ESP32C2
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default n if !IDF_TARGET_ESP32C2
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select ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD
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config ESP_TASK_WDT_INIT
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bool "Initialize Task Watchdog Timer on startup"
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depends on ESP_TASK_WDT_EN
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default y
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help
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Enabling this option will cause the Task Watchdog Timer to be initialized
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automatically at startup.
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config ESP_TASK_WDT_PANIC
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bool "Invoke panic handler on Task Watchdog timeout"
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depends on ESP_TASK_WDT_INIT
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default n
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help
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If this option is enabled, the Task Watchdog Timer will be configured to
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trigger the panic handler when it times out. This can also be configured
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at run time (see Task Watchdog Timer API Reference)
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config ESP_TASK_WDT_TIMEOUT_S
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int "Task Watchdog timeout period (seconds)"
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depends on ESP_TASK_WDT_INIT
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range 1 60
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default 5
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help
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Timeout period configuration for the Task Watchdog Timer in seconds.
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This is also configurable at run time (see Task Watchdog Timer API Reference)
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config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
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bool "Watch CPU0 Idle Task"
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depends on ESP_TASK_WDT_INIT
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default y
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help
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|
If this option is enabled, the Task Watchdog Timer will watch the CPU0
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Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
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of CPU starvation as the Idle Task not being called is usually a symptom of
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CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
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tasks depend on the Idle Task getting some runtime every now and then.
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config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
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bool "Watch CPU1 Idle Task"
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depends on ESP_TASK_WDT_INIT && !FREERTOS_UNICORE
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default y
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help
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If this option is enabled, the Task Watchdog Timer will wach the CPU1
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Idle Task.
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config ESP_XT_WDT
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bool "Initialize XTAL32K watchdog timer on startup"
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depends on !IDF_TARGET_ESP32 && (ESP_SYSTEM_RTC_EXT_OSC || ESP_SYSTEM_RTC_EXT_XTAL)
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default n
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help
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This watchdog timer can detect oscillation failure of the XTAL32K_CLK. When such a failure
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is detected the hardware can be set up to automatically switch to BACKUP32K_CLK and generate
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an interrupt.
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config ESP_XT_WDT_TIMEOUT
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int "XTAL32K watchdog timeout period"
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depends on ESP_XT_WDT
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range 1 255
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default 200
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help
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Timeout period configuration for the XTAL32K watchdog timer based on RTC_CLK.
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config ESP_XT_WDT_BACKUP_CLK_ENABLE
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bool "Automatically switch to BACKUP32K_CLK when timer expires"
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depends on ESP_XT_WDT
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default y
|
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help
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Enable this to automatically switch to BACKUP32K_CLK as the source of RTC_SLOW_CLK when
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the watchdog timer expires.
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|
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config ESP_PANIC_HANDLER_IRAM
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bool "Place panic handler code in IRAM"
|
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default n
|
|
help
|
|
If this option is disabled (default), the panic handler code is placed in flash not IRAM.
|
|
This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will
|
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automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor
|
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risk, if the flash cache status is also corrupted during the crash.
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If this option is enabled, the panic handler code (including required UART functions) is placed
|
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in IRAM. This may be necessary to debug some complex issues with crashes while flash cache is
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disabled (for example, when writing to SPI flash) or when flash cache is corrupted when an exception
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is triggered.
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config ESP_DEBUG_STUBS_ENABLE
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bool "OpenOCD debug stubs"
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default COMPILER_OPTIMIZATION_LEVEL_DEBUG
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depends on !ESP32_TRAX && !ESP32S2_TRAX && !ESP32S3_TRAX
|
|
help
|
|
Debug stubs are used by OpenOCD to execute pre-compiled onboard code
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|
which does some useful debugging stuff, e.g. GCOV data dump.
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config ESP_DEBUG_OCDAWARE
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bool "Make exception and panic handlers JTAG/OCD aware"
|
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default y
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select FREERTOS_DEBUG_OCDAWARE
|
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help
|
|
The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and
|
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instead of panicking, have the debugger stop on the offending instruction.
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|
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choice ESP_SYSTEM_CHECK_INT_LEVEL
|
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prompt "Interrupt level to use for Interrupt Watchdog and other system checks"
|
|
default ESP_SYSTEM_CHECK_INT_LEVEL_4
|
|
help
|
|
Interrupt level to use for Interrupt Watchdog, IPC_ISR and other system checks.
|
|
|
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config ESP_SYSTEM_CHECK_INT_LEVEL_5
|
|
bool "Level 5 interrupt"
|
|
depends on IDF_TARGET_ESP32
|
|
help
|
|
Using level 5 interrupt for Interrupt Watchdog, IPC_ISR and other system checks.
|
|
|
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config ESP_SYSTEM_CHECK_INT_LEVEL_4
|
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bool "Level 4 interrupt"
|
|
depends on !BTDM_CTRL_HLI
|
|
help
|
|
Using level 4 interrupt for Interrupt Watchdog, IPC_ISR and other system checks.
|
|
endchoice
|
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|
|
# Insert chip-specific system config
|
|
rsource "./port/soc/$IDF_TARGET/Kconfig.system"
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|
|
config ESP_SYSTEM_BROWNOUT_INTR
|
|
bool
|
|
default n
|
|
help
|
|
This config allows to trigger an interrupt when brownout detected. Software restart will be done
|
|
at the end of the default callback.
|
|
Two occasions need to restart the chip with interrupt so far.
|
|
(1). For ESP32 version 1, brown-out reset function doesn't work (see ESP32 errata 3.4).
|
|
So that we must restart from interrupt.
|
|
(2). For special workflow, the chip needs do more things instead of restarting directly. This part
|
|
needs to be done in callback function of interrupt.
|
|
|
|
config ESP_SYSTEM_HW_STACK_GUARD
|
|
bool "Hardware stack guard"
|
|
depends on SOC_ASSIST_DEBUG_SUPPORTED
|
|
default y
|
|
help
|
|
This config allows to trigger a panic interrupt when Stack Pointer register goes out of allocated stack
|
|
memory bounds.
|
|
|
|
config ESP_SYSTEM_BBPLL_RECALIB
|
|
bool "Re-calibration BBPLL at startup"
|
|
depends on IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
|
|
default y
|
|
help
|
|
This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version,
|
|
which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with
|
|
ESP-IDF version v5.2 and above.
|
|
|
|
config ESP_SYSTEM_HW_PC_RECORD
|
|
bool "Hardware PC recording"
|
|
depends on SOC_ASSIST_DEBUG_SUPPORTED
|
|
default y
|
|
help
|
|
This option will enable the PC recording function of assist_debug module. The PC value of the CPU will be
|
|
recorded to PC record register in assist_debug module in real time. When an exception occurs and the CPU
|
|
is reset, this register will be kept, then we can use the recorded PC to debug the causes of the reset.
|
|
endmenu # ESP System Settings
|
|
|
|
menu "IPC (Inter-Processor Call)"
|
|
|
|
config ESP_IPC_TASK_STACK_SIZE
|
|
int "Inter-Processor Call (IPC) task stack size"
|
|
range 512 65536 if !APPTRACE_ENABLE
|
|
range 2048 65536 if APPTRACE_ENABLE
|
|
default 2048 if APPTRACE_ENABLE
|
|
default 1280 if !APPTRACE_ENABLE && IDF_TARGET_ESP32S3
|
|
default 1024
|
|
help
|
|
Configure the IPC tasks stack size. An IPC task runs on each core (in dual core mode), and allows for
|
|
cross-core function calls. See IPC documentation for more details. The default IPC stack size should be
|
|
enough for most common simple use cases. However, users can increase/decrease the stack size to their
|
|
needs.
|
|
|
|
config ESP_IPC_USES_CALLERS_PRIORITY
|
|
bool "IPC runs at caller's priority"
|
|
default y
|
|
depends on !FREERTOS_UNICORE
|
|
help
|
|
If this option is not enabled then the IPC task will keep behavior same as prior to that of ESP-IDF v4.0,
|
|
hence IPC task will run at (configMAX_PRIORITIES - 1) priority.
|
|
|
|
config ESP_IPC_ISR_ENABLE
|
|
bool
|
|
default y if !ESP_SYSTEM_SINGLE_CORE_MODE
|
|
help
|
|
The IPC ISR feature is similar to the IPC feature except that the callback function is executed in the
|
|
context of a High Priority Interrupt. The IPC ISR feature is intended for low latency execution of simple
|
|
callbacks written in assembly on another CPU. Due to being run in a High Priority Interrupt, the assembly
|
|
callbacks must be written with particular restrictions (see "IPC" and "High-Level Interrupt" docs for more
|
|
details).
|
|
|
|
endmenu # "IPC (Inter-Processor Call)
|