kopia lustrzana https://github.com/espressif/esp-idf
292 wiersze
11 KiB
C
292 wiersze
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp32c6/rom/ets_sys.h"
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#include "soc/rtc.h"
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#include "soc/pcr_reg.h"
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#include "hal/lp_timer_hal.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/timer_ll.h"
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#include "soc/timer_group_reg.h"
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#include "esp_rom_sys.h"
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#include "assert.h"
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#include "hal/efuse_hal.h"
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#include "soc/chip_revision.h"
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#include "esp_private/periph_ctrl.h"
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static const char *TAG = "rtc_time";
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/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
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* This feature counts the number of XTAL clock cycles within a given number of
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* RTC_SLOW_CLK cycles.
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*
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* Slow clock calibration feature has two modes of operation: one-off and cycling.
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* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
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* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
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* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
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* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
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* enabled using TIMG_RTC_CALI_START bit.
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*/
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/* On ESP32C6, TIMG_RTC_CALI_CLK_SEL can config to 0, 1, 2, 3
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* 0 or 3: calibrate RC_SLOW clock
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* 1: calibrate RC_FAST clock
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* 2: calibrate 32K clock, which 32k depends on reg_32k_sel: 0: Internal 32 kHz RC oscillator, 1: External 32 kHz XTAL, 2: External 32kHz clock input by lp_pad_gpio0
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*/
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#define TIMG_RTC_CALI_CLK_SEL_RC_SLOW 0
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#define TIMG_RTC_CALI_CLK_SEL_RC_FAST 1
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#define TIMG_RTC_CALI_CLK_SEL_32K 2
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/**
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* @brief Clock calibration function used by rtc_clk_cal
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*
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* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
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* This feature counts the number of XTAL clock cycles within a given number of
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* RTC_SLOW_CLK cycles.
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*
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* Slow clock calibration feature has two modes of operation: one-off and cycling.
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* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
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* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
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* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
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* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
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* enabled using TIMG_RTC_CALI_START bit.
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*
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* @param cal_clk which clock to calibrate
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* @param slowclk_cycles number of slow clock cycles to count
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* @return number of XTAL clock cycles within the given number of slow clock cycles
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*/
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static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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{
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assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
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uint32_t cali_clk_sel = 0;
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soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
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soc_rtc_slow_clk_src_t old_32k_cal_clk_sel = clk_ll_32k_calibration_get_target();
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if (cal_clk == RTC_CAL_RTC_MUX) {
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cal_clk = (rtc_cal_sel_t)slow_clk_src;
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}
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if (cal_clk == RTC_CAL_RC_FAST) {
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cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_FAST;
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} else if (cal_clk == RTC_CAL_RC_SLOW) {
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cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_SLOW;
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} else {
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cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_32K;
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clk_ll_32k_calibration_set_target((soc_rtc_slow_clk_src_t)cal_clk);
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}
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/* Enable requested clock (150k clock is always on) */
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// All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock
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// Only enable if orignally was disabled, and set back to the disable state after calibration is done
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// If the clock is already on, then do nothing
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bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
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if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
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clk_ll_xtal32k_digi_enable();
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}
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bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
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bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
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if (cal_clk == RTC_CAL_RC_FAST) {
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if (!rc_fast_enabled) {
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rtc_clk_8m_enable(true);
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}
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if (!dig_rc_fast_enabled) {
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rtc_dig_clk8m_enable();
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}
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}
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bool rc32k_enabled = clk_ll_rc32k_is_enabled();
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bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
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if (cal_clk == RTC_CAL_RC32K) {
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if (!rc32k_enabled) {
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rtc_clk_rc32k_enable(true);
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}
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if (!dig_rc32k_enabled) {
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clk_ll_rc32k_digi_enable();
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}
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}
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/* There may be another calibration process already running during we call this function,
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* so we should wait the last process is done.
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*/
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if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
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/**
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* Set a small timeout threshold to accelerate the generation of timeout.
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* The internal circuit will be reset when the timeout occurs and will not affect the next calibration.
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*/
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REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1);
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while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
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&& !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
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}
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/* Prepare calibration */
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
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/* Figure out how long to wait for calibration to finish */
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/* Set timeout reg and expect time delay*/
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uint32_t expected_freq;
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if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_32K) {
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REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
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expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
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} else if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) {
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REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(slowclk_cycles));
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expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
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} else {
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REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles));
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expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
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}
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uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
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/* Start calibration */
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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/* Wait for calibration to finish up to another us_time_estimate */
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esp_rom_delay_us(us_time_estimate);
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uint32_t cal_val;
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while (true) {
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if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
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cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
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/*The Fosc CLK of calibration circuit is divided by 32 for ECO1.
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So we need to multiply the frequency of the Fosc for ECO1 and above chips by 32 times.
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And ensure that this modification will not affect ECO0.
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And the 32-divider belongs to REF_TICK module, so we need to enable its clock during
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calibration. */
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if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
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if (cal_clk == RTC_CAL_RC_FAST) {
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cal_val = cal_val >> 5;
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CLEAR_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
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}
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}
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break;
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}
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if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
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cal_val = 0;
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break;
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}
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}
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
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if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
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clk_ll_xtal32k_digi_disable();
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}
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if (cal_clk == RTC_CAL_RC_FAST) {
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if (!dig_rc_fast_enabled) {
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rtc_dig_clk8m_disable();
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}
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if (!rc_fast_enabled) {
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rtc_clk_8m_enable(false);
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}
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}
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if (cal_clk == RTC_CAL_RC32K) {
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if (!dig_rc32k_enabled) {
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clk_ll_rc32k_digi_disable();
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}
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if (!rc32k_enabled) {
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rtc_clk_rc32k_enable(false);
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}
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}
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// Always set back the calibration 32kHz clock selection
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if (old_32k_cal_clk_sel != SOC_RTC_SLOW_CLK_SRC_INVALID) {
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clk_ll_32k_calibration_set_target(old_32k_cal_clk_sel);
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}
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return cal_val;
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}
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static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
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{
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uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
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uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 = 0.05% error range
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return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
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}
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uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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{
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assert(slowclk_cycles);
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soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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/*The Fosc CLK of calibration circuit is divided by 32 for ECO1.
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So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
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avoid excessive calibration time.*/
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if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
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if (cal_clk == RTC_CAL_RC_FAST) {
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slowclk_cycles = slowclk_cycles >> 5;
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SET_PERI_REG_MASK(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
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}
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}
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uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
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if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
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return 0;
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}
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uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
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uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
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uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
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return period;
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}
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uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
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{
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assert(period);
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/* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
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* TODO: fix overflow.
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*/
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return (time_in_us << RTC_CLK_CAL_FRACT) / period;
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}
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uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
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{
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return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
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}
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uint64_t rtc_time_get(void)
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{
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return lp_timer_hal_get_cycle_count();
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}
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void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
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{
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// TODO: IDF-5781
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ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
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}
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uint32_t rtc_clk_freq_cal(uint32_t cal_val)
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{
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if (cal_val == 0) {
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return 0; // cal_val will be denominator, return 0 as the symbol of failure.
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}
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return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
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}
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/// @brief if the calibration is used, we need to enable the timer group0 first
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__attribute__((constructor))
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static void enable_timer_group0_for_calibration(void)
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{
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#ifndef BOOTLOADER_BUILD
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PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) {
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if (ref_count == 0) {
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timer_ll_enable_bus_clock(0, true);
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timer_ll_reset_register(0);
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}
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}
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#else
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// no critical section is needed for bootloader
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int __DECLARE_RCC_RC_ATOMIC_ENV;
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timer_ll_enable_bus_clock(0, true);
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timer_ll_reset_register(0);
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#endif
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}
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