kopia lustrzana https://github.com/espressif/esp-idf
250 wiersze
7.5 KiB
C
250 wiersze
7.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "soc/soc.h"
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#include "soc/system_struct.h"
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#include "soc/usb_wrap_struct.h"
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#include "soc/rtc_cntl_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ---------------------------- USB PHY Control ---------------------------- */
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/**
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* @brief Enables and sets the override value for the session end signal
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*
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* @param hw Start address of the USB Wrap registers
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* @param sessend Session end override value. True means VBus < 0.2V, false means VBus > 0.8V
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_srp_sessend_override(usb_wrap_dev_t *hw, bool sessend)
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{
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hw->otg_conf.srp_sessend_value = sessend;
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hw->otg_conf.srp_sessend_override = 1;
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}
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/**
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* @brief Disable session end override
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*
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* @param hw Start address of the USB Wrap registers
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_disable_srp_sessend_override(usb_wrap_dev_t *hw)
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{
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hw->otg_conf.srp_sessend_override = 0;
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}
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/**
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* @brief Sets whether the USB Wrap's FSLS PHY interface routes to an internal or external PHY
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*
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* @param hw Start address of the USB Wrap registers
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* @param enable Enables external PHY, internal otherwise
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_external(usb_wrap_dev_t *hw, bool enable)
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{
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hw->otg_conf.phy_sel = enable;
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// Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY
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RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
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/*
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For 'sw_usb_phy_sel':
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0 - Internal USB FSLS PHY is mapped to the USJ. USB Wrap mapped to external PHY
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1 - Internal USB FSLS PHY is mapped to the USB Wrap. USJ mapped to external PHY
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*/
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RTCCNTL.usb_conf.sw_usb_phy_sel = !enable;
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}
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/**
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* @brief Enables/disables exchanging of the D+/D- pins USB PHY
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*
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* @param hw Start address of the USB Wrap registers
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* @param enable Enables pin exchange, disabled otherwise
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_pin_exchg(usb_wrap_dev_t *hw, bool enable)
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{
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if (enable) {
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hw->otg_conf.exchg_pins = 1;
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hw->otg_conf.exchg_pins_override = 1;
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} else {
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hw->otg_conf.exchg_pins_override = 0;
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hw->otg_conf.exchg_pins = 0;
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}
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}
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/**
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* @brief Enables and sets voltage threshold overrides for USB FSLS PHY single-ended inputs
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*
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* @param hw Start address of the USB Wrap registers
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* @param vrefh_step High voltage threshold. 0 to 3 indicating 80mV steps from 1.76V to 2V.
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* @param vrefl_step Low voltage threshold. 0 to 3 indicating 80mV steps from 0.8V to 1.04V.
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_vref_override(usb_wrap_dev_t *hw, unsigned int vrefh_step, unsigned int vrefl_step)
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{
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hw->otg_conf.vrefh = vrefh_step;
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hw->otg_conf.vrefl = vrefl_step;
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hw->otg_conf.vref_override = 1;
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}
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/**
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* @brief Disables voltage threshold overrides for USB FSLS PHY single-ended inputs
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*
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* @param hw Start address of the USB Wrap registers
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_disable_vref_override(usb_wrap_dev_t *hw)
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{
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hw->otg_conf.vref_override = 0;
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}
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/**
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* @brief Enable override of USB FSLS PHY's pull up/down resistors
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*
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* @param hw Start address of the USB Wrap registers
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* @param dp_pu Enable D+ pullup
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* @param dm_pu Enable D- pullup
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* @param dp_pd Enable D+ pulldown
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* @param dm_pd Enable D- pulldown
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_pull_override(usb_wrap_dev_t *hw, bool dp_pu, bool dm_pu, bool dp_pd, bool dm_pd)
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{
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hw->otg_conf.dp_pullup = dp_pu;
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hw->otg_conf.dp_pulldown = dp_pd;
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hw->otg_conf.dm_pullup = dm_pu;
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hw->otg_conf.dm_pulldown = dm_pd;
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hw->otg_conf.pad_pull_override = 1;
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}
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/**
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* @brief Disable override of USB FSLS PHY pull up/down resistors
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*
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* @param hw Start address of the USB Wrap registers
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_disable_pull_override(usb_wrap_dev_t *hw)
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{
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hw->otg_conf.pad_pull_override = 0;
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}
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/**
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* @brief Sets the strength of the pullup resistor
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*
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* @param hw Start address of the USB Wrap registers
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* @param strong True is a ~1.4K pullup, false is a ~2.4K pullup
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_set_pullup_strength(usb_wrap_dev_t *hw, bool strong)
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{
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hw->otg_conf.pullup_value = strong;
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}
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/**
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* @brief Check if USB FSLS PHY pads are enabled
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*
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* @param hw Start address of the USB Wrap registers
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* @return True if enabled, false otherwise
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*/
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FORCE_INLINE_ATTR bool usb_wrap_ll_phy_is_pad_enabled(usb_wrap_dev_t *hw)
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{
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return hw->otg_conf.pad_enable;
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}
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/**
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* @brief Enable the USB FSLS PHY pads
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*
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* @param hw Start address of the USB Wrap registers
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* @param enable Whether to enable the USB FSLS PHY pads
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_pad(usb_wrap_dev_t *hw, bool enable)
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{
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hw->otg_conf.pad_enable = enable;
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}
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/**
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* @brief Set USB FSLS PHY TX output clock edge
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*
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* @param hw Start address of the USB Wrap registers
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* @param clk_neg_edge True if TX output at negedge, posedge otherwise
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_set_tx_edge(usb_wrap_dev_t *hw, bool clk_neg_edge)
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{
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hw->otg_conf.phy_tx_edge_sel = clk_neg_edge;
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}
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/* ------------------------------ USB PHY Test ------------------------------ */
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/**
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* @brief Enable the USB FSLS PHY's test mode
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*
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* @param hw Start address of the USB Wrap registers
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* @param enable Whether to enable the USB FSLS PHY's test mode
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_test_mode(usb_wrap_dev_t *hw, bool enable)
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{
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hw->test_conf.test_enable = enable;
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}
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/**
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* @brief Set the USB FSLS PHY's signal test values
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*
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* @param hw Start address of the USB Wrap registers
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* @param oen Output Enable (active low) signal
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* @param tx_dp TX D+
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* @param tx_dm TX D-
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* @param rx_dp RX D+
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* @param rx_dm RX D-
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* @param rx_rcv RX RCV
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_phy_test_mode_set_signals(usb_wrap_dev_t *hw,
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bool oen,
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bool tx_dp,
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bool tx_dm,
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bool rx_dp,
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bool rx_dm,
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bool rx_rcv)
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{
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usb_wrap_test_conf_reg_t test_conf;
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test_conf.val = hw->test_conf.val;
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test_conf.test_usb_wrap_oe = oen;
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test_conf.test_tx_dp = tx_dp;
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test_conf.test_tx_dm = tx_dm;
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test_conf.test_rx_rcv = rx_rcv;
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test_conf.test_rx_dp = rx_dp;
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test_conf.test_rx_dm = rx_dm;
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hw->test_conf.val = test_conf.val;
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}
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/* ----------------------------- RCC Functions ----------------------------- */
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/**
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* Enable the bus clock for USB Wrap module
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* @param clk_en True if enable the clock of USB Wrap module
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_enable_bus_clock(bool clk_en)
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{
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SYSTEM.perip_clk_en0.usb_clk_en = clk_en;
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}
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// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
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#define usb_wrap_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_wrap_ll_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the USB Wrap module
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*/
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FORCE_INLINE_ATTR void usb_wrap_ll_reset_register(void)
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{
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SYSTEM.perip_rst_en0.usb_rst = 1;
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SYSTEM.perip_rst_en0.usb_rst = 0;
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}
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// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
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#define usb_wrap_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_wrap_ll_reset_register(__VA_ARGS__)
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#ifdef __cplusplus
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}
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#endif
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