kopia lustrzana https://github.com/espressif/esp-idf
357 wiersze
10 KiB
C
357 wiersze
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer of the USB-serial-jtag controller
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#pragma once
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "soc/system_struct.h"
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#include "soc/rtc_cntl_struct.h"
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#include "soc/usb_serial_jtag_reg.h"
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#include "soc/usb_serial_jtag_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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//The in and out endpoints are this long.
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#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64
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#define USB_SERIAL_JTAG_LL_INTR_MASK (0x7ffff) //All interrupt mask
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// Define USB_SERIAL_JTAG interrupts
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// Note the hardware has more interrupts, but they're only useful for debugging
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// the hardware.
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typedef enum {
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USB_SERIAL_JTAG_INTR_SOF = (1 << 1),
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USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT = (1 << 2),
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USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY = (1 << 3),
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USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1 = (1 << 8),
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USB_SERIAL_JTAG_INTR_BUS_RESET = (1 << 9),
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USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD = (1 << 10),
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} usb_serial_jtag_intr_t;
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/* ----------------------------- USJ Peripheral ----------------------------- */
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/**
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* @brief Enable the USB_SERIAL_JTAG interrupt based on the given mask.
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*
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* @param mask The bitmap of the interrupts need to be enabled.
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*
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* @return None
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*/
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static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask)
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{
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USB_SERIAL_JTAG.int_ena.val |= mask;
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}
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/**
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* @brief Disable the USB_SERIAL_JTAG interrupt based on the given mask.
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*
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* @param mask The bitmap of the interrupts need to be disabled.
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*
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* @return None
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*/
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static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask)
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{
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USB_SERIAL_JTAG.int_ena.val &= (~mask);
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}
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/**
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* @brief Get the USB_SERIAL_JTAG interrupt status.
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*
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* @return The USB_SERIAL_JTAG interrupt status.
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*/
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static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void)
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{
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return USB_SERIAL_JTAG.int_st.val;
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}
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/**
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* @brief Get the USB_SERIAL_JTAG raw interrupt status.
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*
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* @return The USB_SERIAL_JTAG raw interrupt status.
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*/
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static inline __attribute__((always_inline)) uint32_t usb_serial_jtag_ll_get_intraw_mask(void)
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{
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return USB_SERIAL_JTAG.int_raw.val;
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}
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/**
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* @brief Clear the USB_SERIAL_JTAG interrupt status based on the given mask.
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*
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* @param mask The bitmap of the interrupts need to be cleared.
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*
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* @return None
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*/
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static inline __attribute__((always_inline)) void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask)
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{
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USB_SERIAL_JTAG.int_clr.val = mask;
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}
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/**
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* @brief Get status of enabled interrupt.
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*
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* @return interrupt enable value
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*/
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static inline uint32_t usb_serial_jtag_ll_get_intr_ena_status(void)
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{
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return USB_SERIAL_JTAG.int_ena.val;
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}
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/**
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* @brief Read the bytes from the USB_SERIAL_JTAG rxfifo.
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*
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* @param buf The data buffer.
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* @param rd_len The data length needs to be read.
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*
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* @return amount of bytes read
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*/
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static inline uint32_t usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
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{
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uint32_t i;
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for (i = 0; i < rd_len; i++) {
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if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
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buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
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}
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return i;
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}
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/**
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* @brief Write byte to the USB_SERIAL_JTAG txfifo. Only writes bytes as long / if there
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* is room in the buffer.
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*
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* @param buf The data buffer.
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* @param wr_len The data length needs to be writen.
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*
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* @return Amount of bytes actually written. May be less than wr_len.
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*/
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static inline uint32_t usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t wr_len)
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{
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uint32_t i;
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for (i = 0; i < wr_len; i++) {
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if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
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USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
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}
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return i;
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}
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/**
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* @brief Returns 1 if the USB_SERIAL_JTAG rxfifo has data available.
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*
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* @return 0 if no data available, 1 if data available
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*/
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static inline int usb_serial_jtag_ll_rxfifo_data_available(void)
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{
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return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail;
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}
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/**
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* @brief Returns 1 if the USB_SERIAL_JTAG txfifo has room.
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*
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* @return 0 if no data available, 1 if data available
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*/
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static inline int usb_serial_jtag_ll_txfifo_writable(void)
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{
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return USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free;
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}
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/**
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* @brief Flushes the TX buffer, that is, make it available for the
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* host to pick up.
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*
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* @note When fifo is full (with 64 byte), HW will flush the buffer automatically,
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* if this function is called directly after, this effectively turns into a
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* no-op. Because a 64-byte packet will be interpreted as a not-complete USB
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* transaction, you need to transfer either more data or a zero-length packet
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* for the data to actually end up at the program listening to the CDC-ACM
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* serial port. To send a zero-length packet, call
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* usb_serial_jtag_ll_txfifo_flush() again when
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* usb_serial_jtag_ll_txfifo_writable() returns true.
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*
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* @return na
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*/
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static inline void usb_serial_jtag_ll_txfifo_flush(void)
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{
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USB_SERIAL_JTAG.ep1_conf.wr_done=1;
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}
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/**
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* @brief Enable USJ JTAG bridge
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*
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* If enabled, USJ is disconnected from internal JTAG interface. JTAG interface
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* is routed through GPIO matrix instead.
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*
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* @param enable Enable USJ JTAG bridge
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_jtag_bridge(bool enable)
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{
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USB_SERIAL_JTAG.conf0.usb_jtag_bridge_en = enable;
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}
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/* ---------------------------- USB PHY Control ---------------------------- */
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/**
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* @brief Sets whether the USJ's FSLS PHY interface routes to an internal or external PHY
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*
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* @param enable Enables external PHY, internal otherwise
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_external(bool enable)
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{
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USB_SERIAL_JTAG.conf0.phy_sel = enable;
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// Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY
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RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
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/*
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For 'sw_usb_phy_sel':
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0 - Internal USB FSLS PHY is mapped to the USJ. USB Wrap mapped to external PHY
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1 - Internal USB FSLS PHY is mapped to the USB Wrap. USJ mapped to external PHY
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*/
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RTCCNTL.usb_conf.sw_usb_phy_sel = enable;
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}
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/**
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* @brief Enables/disables exchanging of the D+/D- pins USB PHY
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*
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* @param enable Enables pin exchange, disabled otherwise
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pin_exchg(bool enable)
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{
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if (enable) {
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USB_SERIAL_JTAG.conf0.exchg_pins = 1;
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USB_SERIAL_JTAG.conf0.exchg_pins_override = 1;
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} else {
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USB_SERIAL_JTAG.conf0.exchg_pins_override = 0;
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USB_SERIAL_JTAG.conf0.exchg_pins = 0;
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}
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}
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/**
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* @brief Enables and sets voltage threshold overrides for USB FSLS PHY single-ended inputs
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*
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* @param vrefh_step High voltage threshold. 0 to 3 indicating 80mV steps from 1.76V to 2V.
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* @param vrefl_step Low voltage threshold. 0 to 3 indicating 80mV steps from 0.8V to 1.04V.
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_vref_override(unsigned int vrefh_step, unsigned int vrefl_step)
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{
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USB_SERIAL_JTAG.conf0.vrefh = vrefh_step;
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USB_SERIAL_JTAG.conf0.vrefl = vrefl_step;
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USB_SERIAL_JTAG.conf0.vref_override = 1;
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}
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/**
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* @brief Disables voltage threshold overrides for USB FSLS PHY single-ended inputs
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_vref_override(void)
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{
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USB_SERIAL_JTAG.conf0.vref_override = 0;
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}
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/**
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* @brief Enable override of USB FSLS PHY's pull up/down resistors
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*
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* @param dp_pu Enable D+ pullup
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* @param dm_pu Enable D- pullup
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* @param dp_pd Enable D+ pulldown
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* @param dm_pd Enable D- pulldown
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pull_override(bool dp_pu, bool dm_pu, bool dp_pd, bool dm_pd)
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{
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USB_SERIAL_JTAG.conf0.dp_pullup = dp_pu;
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USB_SERIAL_JTAG.conf0.dp_pulldown = dp_pd;
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USB_SERIAL_JTAG.conf0.dm_pullup = dm_pu;
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USB_SERIAL_JTAG.conf0.dm_pulldown = dm_pd;
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USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
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}
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/**
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* @brief Disable override of USB FSLS PHY pull up/down resistors
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_pull_override(void)
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{
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USB_SERIAL_JTAG.conf0.pad_pull_override = 0;
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}
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/**
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* @brief Sets the strength of the pullup resistor
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*
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* @param strong True is a ~1.4K pullup, false is a ~2.4K pullup
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_pullup_strength(bool strong)
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{
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USB_SERIAL_JTAG.conf0.pullup_value = strong;
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}
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/**
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* @brief Check if USB FSLS PHY pads are enabled
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*
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* @return True if enabled, false otherwise
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*/
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FORCE_INLINE_ATTR bool usb_serial_jtag_ll_phy_is_pad_enabled(void)
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{
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return USB_SERIAL_JTAG.conf0.usb_pad_enable;
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}
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/**
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* @brief Enable the USB FSLS PHY pads
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*
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* @param enable Whether to enable the USB FSLS PHY pads
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pad(bool enable)
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{
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USB_SERIAL_JTAG.conf0.usb_pad_enable = enable;
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}
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/**
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* @brief Set USB FSLS PHY TX output clock edge
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*
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* @param clk_neg_edge True if TX output at negedge, posedge otherwise
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_tx_edge(bool clk_neg_edge)
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{
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USB_SERIAL_JTAG.conf0.phy_tx_edge_sel = clk_neg_edge;
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}
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/* ----------------------------- RCC Functions ----------------------------- */
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/**
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* @brief Enable the bus clock for USB Serial_JTAG module
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* @param clk_en True if enable the clock of USB Serial_JTAG module
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*/
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FORCE_INLINE_ATTR void _usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
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{
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SYSTEM.perip_clk_en1.usb_device_clk_en = clk_en;
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}
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// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
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#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the usb serial jtag module
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void)
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{
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SYSTEM.perip_rst_en1.usb_device_rst = 1;
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SYSTEM.perip_rst_en1.usb_device_rst = 0;
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}
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// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
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#define usb_serial_jtag_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_serial_jtag_ll_reset_register(__VA_ARGS__)
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/**
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* Get the enable status USB Serial_JTAG module
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*
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* @return Return true if USB Serial_JTAG module is enabled
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*/
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FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void)
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{
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return (SYSTEM.perip_clk_en1.usb_device_clk_en && !SYSTEM.perip_rst_en1.usb_device_rst);
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}
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#ifdef __cplusplus
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}
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#endif
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