kopia lustrzana https://github.com/espressif/esp-idf
141 wiersze
6.0 KiB
C
141 wiersze
6.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "hal/adc_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief ADC resolution setting option.
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* @note Only used in single read mode
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*/
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typedef enum {
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#if CONFIG_IDF_TARGET_ESP32
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ADC_WIDTH_BIT_9 = 9, /*!< ADC capture width is 9Bit. */
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ADC_WIDTH_BIT_10 = 10, /*!< ADC capture width is 10Bit. */
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ADC_WIDTH_BIT_11 = 11, /*!< ADC capture width is 11Bit. */
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ADC_WIDTH_BIT_12 = 12, /*!< ADC capture width is 12Bit. */
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#elif SOC_ADC_RTC_MAX_BITWIDTH == 12
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ADC_WIDTH_BIT_12 = 12, /*!< ADC capture width is 12Bit. */
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#elif SOC_ADC_RTC_MAX_BITWIDTH == 13
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ADC_WIDTH_BIT_13 = 13, /*!< ADC capture width is 13Bit. */
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#endif
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ADC_WIDTH_MAX,
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} adc_bits_width_t;
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/**
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* The default (max) bit width of the ADC of current version. You can also get the maximum bitwidth
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* by `SOC_ADC_RTC_MAX_BITWIDTH` defined in soc_caps.h.
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*/
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#define ADC_WIDTH_BIT_DEFAULT (ADC_WIDTH_MAX-1)
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#if CONFIG_IDF_TARGET_ESP32
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typedef enum {
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ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO36 */
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ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO37 */
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ADC1_CHANNEL_2, /*!< ADC1 channel 2 is GPIO38 */
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ADC1_CHANNEL_3, /*!< ADC1 channel 3 is GPIO39 */
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ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO32 */
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ADC1_CHANNEL_5, /*!< ADC1 channel 5 is GPIO33 */
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ADC1_CHANNEL_6, /*!< ADC1 channel 6 is GPIO34 */
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ADC1_CHANNEL_7, /*!< ADC1 channel 7 is GPIO35 */
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ADC1_CHANNEL_MAX,
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} adc1_channel_t;
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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typedef enum {
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ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO1 */
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ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO2 */
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ADC1_CHANNEL_2, /*!< ADC1 channel 2 is GPIO3 */
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ADC1_CHANNEL_3, /*!< ADC1 channel 3 is GPIO4 */
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ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO5 */
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ADC1_CHANNEL_5, /*!< ADC1 channel 5 is GPIO6 */
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ADC1_CHANNEL_6, /*!< ADC1 channel 6 is GPIO7 */
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ADC1_CHANNEL_7, /*!< ADC1 channel 7 is GPIO8 */
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ADC1_CHANNEL_8, /*!< ADC1 channel 8 is GPIO9 */
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ADC1_CHANNEL_9, /*!< ADC1 channel 9 is GPIO10 */
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ADC1_CHANNEL_MAX,
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} adc1_channel_t;
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
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typedef enum {
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ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
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ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */
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ADC1_CHANNEL_2, /*!< ADC1 channel 2 is GPIO2 */
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ADC1_CHANNEL_3, /*!< ADC1 channel 3 is GPIO3 */
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ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO4 */
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ADC1_CHANNEL_MAX,
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} adc1_channel_t;
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#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
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typedef enum {
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ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
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ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */
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ADC1_CHANNEL_2, /*!< ADC1 channel 2 is GPIO2 */
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ADC1_CHANNEL_3, /*!< ADC1 channel 3 is GPIO3 */
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ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO4 */
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ADC1_CHANNEL_5, /*!< ADC1 channel 5 is GPIO5 */
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ADC1_CHANNEL_6, /*!< ADC1 channel 6 is GPIO6 */
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ADC1_CHANNEL_MAX,
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} adc1_channel_t;
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#endif // CONFIG_IDF_TARGET_*
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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typedef enum {
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ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO4 (ESP32), GPIO11 (ESP32-S2) */
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ADC2_CHANNEL_1, /*!< ADC2 channel 1 is GPIO0 (ESP32), GPIO12 (ESP32-S2) */
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ADC2_CHANNEL_2, /*!< ADC2 channel 2 is GPIO2 (ESP32), GPIO13 (ESP32-S2) */
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ADC2_CHANNEL_3, /*!< ADC2 channel 3 is GPIO15 (ESP32), GPIO14 (ESP32-S2) */
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ADC2_CHANNEL_4, /*!< ADC2 channel 4 is GPIO13 (ESP32), GPIO15 (ESP32-S2) */
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ADC2_CHANNEL_5, /*!< ADC2 channel 5 is GPIO12 (ESP32), GPIO16 (ESP32-S2) */
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ADC2_CHANNEL_6, /*!< ADC2 channel 6 is GPIO14 (ESP32), GPIO17 (ESP32-S2) */
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ADC2_CHANNEL_7, /*!< ADC2 channel 7 is GPIO27 (ESP32), GPIO18 (ESP32-S2) */
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ADC2_CHANNEL_8, /*!< ADC2 channel 8 is GPIO25 (ESP32), GPIO19 (ESP32-S2) */
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ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 (ESP32), GPIO20 (ESP32-S2) */
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ADC2_CHANNEL_MAX,
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} adc2_channel_t;
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
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// ESP32C6 has no ADC2
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typedef enum {
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ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO5 */
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ADC2_CHANNEL_MAX,
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} adc2_channel_t;
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#endif
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#if SOC_ADC_DMA_SUPPORTED
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/**
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* @brief Digital ADC DMA read max timeout value, it may make the ``adc_digi_read_bytes`` block forever if the OS supports
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*/
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#define ADC_MAX_DELAY UINT32_MAX
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/**
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* @brief ADC DMA driver configuration
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*/
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typedef struct adc_digi_init_config_s {
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uint32_t max_store_buf_size; ///< Max length of the converted data that driver can store before they are processed.
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uint32_t conv_num_each_intr; ///< Bytes of data that can be converted in 1 interrupt. This should be in multiples of `SOC_ADC_DIGI_DATA_BYTES_PER_CONV`.
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uint32_t adc1_chan_mask; ///< Channel list of ADC1 to be initialized.
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uint32_t adc2_chan_mask; ///< Channel list of ADC2 to be initialized.
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} adc_digi_init_config_t;
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/**
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* @brief ADC digital controller settings
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*/
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typedef struct {
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bool conv_limit_en; ///< Suggest leaving it empty, this parameter has been deprecated
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uint32_t conv_limit_num; ///< suggest leaving it empty, this parameter has been deprecated
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uint32_t pattern_num; ///< Number of ADC channels that will be used
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adc_digi_pattern_config_t *adc_pattern; ///< List of configs for each ADC channel that will be used
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uint32_t sample_freq_hz; /*!< Please refer to `soc/soc_caps.h` to know the ADC sampling frequency range*/
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adc_digi_convert_mode_t conv_mode; ///< ADC DMA conversion mode, see `adc_digi_convert_mode_t`.
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adc_digi_output_format_t format; ///< ADC DMA conversion output format, see `adc_digi_output_format_t`.
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} adc_digi_configuration_t;
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#endif // #if SOC_ADC_DMA_SUPPORTED
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#ifdef __cplusplus
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}
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#endif
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