kopia lustrzana https://github.com/espressif/esp-idf
344 wiersze
10 KiB
C
344 wiersze
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_image_format.h"
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#include "flash_qio_mode.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "esp_rom_uart.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_spiflash.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/io_mux_reg.h"
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#include "soc/assist_debug_reg.h"
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#include "esp_cpu.h"
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#include "soc/rtc.h"
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#include "soc/spi_periph.h"
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#include "soc/extmem_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/pcr_reg.h"
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#include "esp32c6/rom/efuse.h"
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#include "esp32c6/rom/ets_sys.h"
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#include "esp32c6/rom/spi_flash.h"
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#include "bootloader_common.h"
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#include "bootloader_init.h"
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#include "bootloader_clock.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_mem.h"
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#include "esp_private/regi2c_ctrl.h"
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#include "soc/regi2c_lp_bias.h"
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#include "soc/regi2c_bias.h"
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#include "bootloader_console.h"
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#include "bootloader_flash_priv.h"
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#include "bootloader_soc.h"
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#include "esp_efuse.h"
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#include "hal/mmu_hal.h"
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#include "hal/cache_hal.h"
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#include "hal/clk_tree_ll.h"
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#include "soc/lp_wdt_reg.h"
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#include "hal/efuse_hal.h"
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#include "modem/modem_lpcon_reg.h"
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static const char *TAG = "boot.esp32c6";
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void IRAM_ATTR bootloader_configure_spi_pins(int drv)
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{
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uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
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uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
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uint8_t d_gpio_num = SPI_D_GPIO_NUM;
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uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
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uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
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uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
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esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
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}
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static void update_flash_config(const esp_image_header_t *bootloader_hdr)
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{
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uint32_t size;
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switch (bootloader_hdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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size = 1;
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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size = 2;
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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size = 4;
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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size = 8;
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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size = 16;
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break;
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default:
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size = 2;
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}
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cache_hal_disable(CACHE_TYPE_ALL);
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// Set flash chip size
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esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
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cache_hal_enable(CACHE_TYPE_ALL);
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}
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static void print_flash_info(const esp_image_header_t *bootloader_hdr)
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{
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ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
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ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
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ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
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ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
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ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
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const char *str;
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switch (bootloader_hdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_DIV_2:
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str = "40MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_3:
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str = "26.7MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_4:
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str = "20MHz";
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_1:
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str = "80MHz";
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break;
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default:
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str = "20MHz";
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break;
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}
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ESP_LOGI(TAG, "SPI Speed : %s", str);
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/* SPI mode could have been set to QIO during boot already,
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so test the SPI registers not the flash header */
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uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
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if (spi_ctrl & SPI_MEM_FREAD_QIO) {
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str = "QIO";
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} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
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str = "QOUT";
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} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
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str = "DIO";
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} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
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str = "DOUT";
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} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
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str = "FAST READ";
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} else {
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str = "SLOW READ";
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}
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ESP_LOGI(TAG, "SPI Mode : %s", str);
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switch (bootloader_hdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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str = "1MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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str = "2MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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str = "4MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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str = "8MB";
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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str = "16MB";
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break;
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default:
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str = "2MB";
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break;
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}
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ESP_LOGI(TAG, "SPI Flash Size : %s", str);
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}
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static void IRAM_ATTR bootloader_init_flash_configure(void)
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{
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bootloader_configure_spi_pins(1);
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bootloader_flash_cs_timing_config();
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}
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static void bootloader_spi_flash_resume(void)
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{
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bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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}
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static esp_err_t bootloader_init_spi_flash(void)
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{
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bootloader_init_flash_configure();
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bootloader_spi_flash_resume();
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bootloader_flash_unlock();
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
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bootloader_enable_qio_mode();
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#endif
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print_flash_info(&bootloader_image_hdr);
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update_flash_config(&bootloader_image_hdr);
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//ensure the flash is write-protected
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bootloader_enable_wp();
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return ESP_OK;
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}
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static void wdt_reset_cpu0_info_enable(void)
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{
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REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN);
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REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN);
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REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
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}
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static void wdt_reset_info_dump(int cpu)
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{
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(void) cpu;
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// saved PC was already printed by the ROM bootloader.
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// nothing to do here.
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}
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static void bootloader_check_wdt_reset(void)
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{
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int wdt_rst = 0;
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soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
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if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
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rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
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ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
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wdt_rst = 1;
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}
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if (wdt_rst) {
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// if reset by WDT dump info from trace port
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wdt_reset_info_dump(0);
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}
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wdt_reset_cpu0_info_enable();
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}
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static void bootloader_super_wdt_auto_feed(void)
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{
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REG_WRITE(LP_WDT_SWD_WPROTECT_REG, LP_WDT_SWD_WKEY_VALUE);
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REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
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REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0);
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}
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static inline void bootloader_hardware_init(void)
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{
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// In 80MHz flash mode, ROM sets the mspi module clk divider to 2, fix it here
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#if CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_APP_BUILD_TYPE_RAM
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clk_ll_mspi_fast_set_hs_divider(6);
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esp_rom_spiflash_config_clk(1, 0);
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esp_rom_spiflash_config_clk(1, 1);
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esp_rom_spiflash_fix_dummylen(0, 1);
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esp_rom_spiflash_fix_dummylen(1, 1);
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#endif
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// TODO: IDF-5990 need update, enable i2c mst clk by force on temporarily
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SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO);
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SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
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}
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static inline void bootloader_ana_reset_config(void)
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{
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// TODO: IDF-5990 copied from C3, need update
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// Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back
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/*
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For origin chip & ECO1: only support swt reset;
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For ECO2: fix brownout reset bug, support swt & brownout reset;
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For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
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*/
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uint8_t chip_version = efuse_hal_get_minor_chip_version();
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switch (chip_version) {
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case 0:
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case 1:
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//Disable BOR and GLITCH reset
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bootloader_ana_bod_reset_config(false);
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bootloader_ana_clock_glitch_reset_config(false);
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break;
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case 2:
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//Enable BOR reset. Disable GLITCH reset
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bootloader_ana_bod_reset_config(true);
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bootloader_ana_clock_glitch_reset_config(false);
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break;
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case 3:
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default:
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//Enable BOR, and GLITCH reset
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bootloader_ana_bod_reset_config(true);
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bootloader_ana_clock_glitch_reset_config(true);
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break;
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}
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}
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esp_err_t bootloader_init(void)
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{
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esp_err_t ret = ESP_OK;
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bootloader_hardware_init();
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bootloader_ana_reset_config();
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bootloader_super_wdt_auto_feed();
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// In RAM_APP, memory will be initialized in `call_start_cpu0`
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#if !CONFIG_APP_BUILD_TYPE_RAM
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// protect memory region
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bootloader_init_mem();
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/* check that static RAM is after the stack */
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assert(&_bss_start <= &_bss_end);
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assert(&_data_start <= &_data_end);
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// clear bss section
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bootloader_clear_bss_section();
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#endif // !CONFIG_APP_BUILD_TYPE_RAM
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// init eFuse virtual mode (read eFuses to RAM)
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#ifdef CONFIG_EFUSE_VIRTUAL
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ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
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#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
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esp_efuse_init_virtual_mode_in_ram();
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#endif
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#endif
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// config clock
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bootloader_clock_configure();
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// initialize console, from now on, we can use esp_log
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bootloader_console_init();
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/* print 2nd bootloader banner */
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bootloader_print_banner();
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#if !CONFIG_APP_BUILD_TYPE_RAM
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//init cache hal
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cache_hal_init();
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//reset mmu
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mmu_hal_init();
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// update flash ID
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bootloader_flash_update_id();
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// Check and run XMC startup flow
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if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
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ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
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return ret;
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}
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// read bootloader header
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if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
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return ret;
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}
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// read chip revision and check if it's compatible to bootloader
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if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
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return ret;
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}
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// initialize spi flash
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if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
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return ret;
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}
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#endif // !CONFIG_APP_BUILD_TYPE_RAM
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// check whether a WDT reset happend
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bootloader_check_wdt_reset();
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// config WDT
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bootloader_config_wdt();
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// enable RNG early entropy source
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bootloader_enable_random();
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return ret;
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}
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