kopia lustrzana https://github.com/espressif/esp-idf
410 wiersze
16 KiB
C
410 wiersze
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2013-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "string.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "esp_bit_defs.h"
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#include "esp_log.h"
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#include "../esp_psram_impl.h"
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#include "esp32s3/rom/spi_flash.h"
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#include "esp32s3/rom/opi_flash.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "hal/gpio_hal.h"
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#include "esp_private/spi_flash_os.h"
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#include "esp_private/mspi_timing_tuning.h"
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#include "esp_private/esp_gpio_reserve.h"
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static const char* TAG = "quad_psram";
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//Commands for PSRAM chip
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#define PSRAM_READ 0x03
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#define PSRAM_FAST_READ 0x0B
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#define PSRAM_FAST_READ_QUAD 0xEB
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#define PSRAM_WRITE 0x02
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#define PSRAM_QUAD_WRITE 0x38
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#define PSRAM_ENTER_QMODE 0x35
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#define PSRAM_EXIT_QMODE 0xF5
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#define PSRAM_RESET_EN 0x66
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#define PSRAM_RESET 0x99
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#define PSRAM_SET_BURST_LEN 0xC0
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#define PSRAM_DEVICE_ID 0x9F
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#define PSRAM_FAST_READ_DUMMY 4
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#define PSRAM_FAST_READ_QUAD_DUMMY 6
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// ID
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#define PSRAM_ID_KGD_M 0xff
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#define PSRAM_ID_KGD_S 8
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#define PSRAM_ID_KGD 0x5d
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#define PSRAM_ID_EID_M 0xff
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#define PSRAM_ID_EID_S 16
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// Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
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//
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// BIT7 | BIT6 | BIT5 | SIZE(MBIT)
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// -------------------------------------
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// 0 | 0 | 0 | 16
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// 0 | 0 | 1 | 32
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// 0 | 1 | 0 | 64
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#define PSRAM_EID_SIZE_M 0x07
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#define PSRAM_EID_SIZE_S 5
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#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
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#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
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#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
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#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
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#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
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// IO-pins for PSRAM.
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// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
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// hardcode the flash pins as well, making this code incompatible with either a setup
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// that has the flash on non-standard pins or ESP32s with built-in flash.
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#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
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#define FLASH_CS_IO SPI_CS0_GPIO_NUM
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// PSRAM clock and cs IO should be configured based on hardware design.
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#define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
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#define PSRAM_CS_IO SPI_CS1_GPIO_NUM
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#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
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#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
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#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
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#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
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#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M
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#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M
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#define SPI1_NUM 1
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#define SPI0_NUM 0
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typedef enum {
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PSRAM_CMD_QPI,
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PSRAM_CMD_SPI,
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} psram_cmd_mode_t;
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typedef esp_rom_spi_cmd_t psram_cmd_t;
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static uint32_t s_psram_id = 0;
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static uint32_t s_psram_size = 0; //this stands for physical psram size in bytes
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static void config_psram_spi_phases(void);
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extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
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static uint8_t s_psram_cs_io = (uint8_t) -1;
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uint8_t esp_psram_impl_get_cs_io(void)
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{
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return s_psram_cs_io;
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}
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static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
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{
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if (mode == PSRAM_CMD_QPI) {
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esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE);
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SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
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} else if (mode == PSRAM_CMD_SPI) {
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esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE);
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}
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}
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static void _psram_exec_cmd(int spi_num,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len)
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{
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esp_rom_spi_cmd_t conf;
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uint32_t _addr = addr;
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conf.addr = &_addr;
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conf.addrBitLen = addr_bit_len;
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conf.cmd = cmd;
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conf.cmdBitLen = cmd_bit_len;
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conf.dummyBitLen = dummy_bits; // There is a hardware approach on chip723
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conf.txData = (uint32_t*) mosi_data;
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conf.txDataBitLen = mosi_bit_len;
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conf.rxData = (uint32_t*) miso_data;
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conf.rxDataBitLen = miso_bit_len;
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esp_rom_spi_cmd_config(spi_num, &conf);
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}
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void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len,
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uint32_t cs_mask,
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bool is_write_erase_operation)
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{
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uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
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uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
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uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num));
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uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num));
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psram_set_op_mode(spi_num, mode);
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_psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
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dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
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esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
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WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
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WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1);
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WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2);
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WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl);
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}
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//exit QPI mode(set back to SPI mode)
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static void psram_disable_qio_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_CMD_QPI,
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PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//TODO IDF-4307
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//switch psram burst length(32 bytes or 1024 bytes)
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//datasheet says it should be 1024 bytes by default
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static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
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{
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psram_exec_cmd(spi_num, mode,
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PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//send reset command to psram, in spi mode
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static void psram_reset_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
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PSRAM_RESET_EN, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
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PSRAM_RESET, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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esp_err_t psram_enable_wrap(uint32_t wrap_size)
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{
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//TODO: IDF-4307
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static uint32_t current_wrap_size = 0;
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if (current_wrap_size == wrap_size) {
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return ESP_OK;
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}
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switch (wrap_size) {
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case 32:
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case 0:
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psram_set_wrap_burst_length(1, PSRAM_CMD_QPI);
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current_wrap_size = wrap_size;
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return ESP_OK;
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case 16:
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case 64:
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default:
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return ESP_FAIL;
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}
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}
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bool psram_support_wrap_size(uint32_t wrap_size)
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{
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switch (wrap_size) {
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case 0:
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case 32:
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return true;
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case 16:
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case 64:
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default:
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return false;
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}
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}
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//Read ID operation only supports SPI CMD and mode, should issue `psram_disable_qio_mode` before calling this
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static void psram_read_id(int spi_num, uint32_t* dev_id)
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{
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psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
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PSRAM_DEVICE_ID, 8, /* command and command bit len*/
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0, 24, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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(uint8_t*) dev_id, 24, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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//enter QPI mode
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static void psram_enable_qio_mode(int spi_num)
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{
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psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
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PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
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0, 0, /* address and address bit len*/
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0, /* dummy bit len */
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NULL, 0, /* tx data and tx bit len*/
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NULL, 0, /* rx data and rx bit len*/
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CS_PSRAM_SEL, /* cs bit mask*/
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false); /* whether is program/erase operation */
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}
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static void psram_set_cs_timing(void)
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{
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//SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers for PSRAM, so we only need to set SPI0 related registers here
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SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S);
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SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M);
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}
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static void psram_gpio_config(void)
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{
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//CS1
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uint8_t cs1_io = PSRAM_CS_IO;
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if (cs1_io == SPI_CS1_GPIO_NUM) {
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], FUNC_SPICS1_SPICS1);
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} else {
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esp_rom_gpio_connect_out_signal(cs1_io, SPICS1_OUT_IDX, 0, 0);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], PIN_FUNC_GPIO);
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}
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s_psram_cs_io = cs1_io;
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//WP HD
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uint8_t wp_io = PSRAM_SPIWP_SD3_IO;
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
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// MSPI pins (except wp / hd) are all configured via IO_MUX in 1st bootloader.
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} else {
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// MSPI pins (except wp / hd) are all configured via GPIO matrix in 1st bootloader.
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wp_io = esp_rom_efuse_get_flash_wp_gpio();
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}
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//This ROM function will init both WP and HD pins.
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esp_rom_spiflash_select_qio_pins(wp_io, spiconfig);
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// Reserve psram pins
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esp_gpio_reserve(BIT64(cs1_io) | BIT64(wp_io));
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}
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esp_err_t esp_psram_impl_enable(void) //psram init
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{
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psram_gpio_config();
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psram_set_cs_timing();
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//enter MSPI slow mode to init PSRAM device registers
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mspi_timing_enter_low_speed_mode(true);
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//We use SPI1 to init PSRAM
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psram_disable_qio_mode(SPI1_NUM);
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psram_read_id(SPI1_NUM, &s_psram_id);
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if (!PSRAM_IS_VALID(s_psram_id)) {
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/* 16Mbit psram ID read error workaround:
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* treat the first read id as a dummy one as the pre-condition,
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* Send Read ID command again
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*/
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psram_read_id(SPI1_NUM, &s_psram_id);
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if (!PSRAM_IS_VALID(s_psram_id)) {
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08" PRIx32 ", PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)s_psram_id);
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return ESP_ERR_NOT_SUPPORTED;
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}
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}
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if (PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
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s_psram_size = PSRAM_SIZE_8MB;
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} else {
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uint8_t density = PSRAM_SIZE_ID(s_psram_id);
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s_psram_size = density == 0x0 ? PSRAM_SIZE_2MB :
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density == 0x1 ? PSRAM_SIZE_4MB :
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density == 0x2 ? PSRAM_SIZE_8MB : 0;
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}
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//SPI1: send psram reset command
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psram_reset_mode(SPI1_NUM);
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//SPI1: send QPI enable command
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psram_enable_qio_mode(SPI1_NUM);
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//Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly
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mspi_timing_psram_tuning();
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//Configure SPI0 PSRAM related SPI Phases
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config_psram_spi_phases();
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//Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
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mspi_timing_enter_high_speed_mode(true);
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return ESP_OK;
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}
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//Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
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static void config_psram_spi_phases(void)
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{
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//Config CMD phase
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CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command
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SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command
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SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read command
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SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache write command
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SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
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SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
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SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
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SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD, SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB
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//Config ADDR phase
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SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S);
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//Dummy
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/**
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* We set the PSRAM chip required dummy here. If timing tuning is needed,
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* the dummy length will be updated in `mspi_timing_enter_high_speed_mode()`
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*/
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SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
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SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (PSRAM_FAST_READ_QUAD_DUMMY - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy
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CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
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}
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/*---------------------------------------------------------------------------------
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* Following APIs are not required to be IRAM-Safe
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*
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* Consider moving these to another file if this kind of APIs grows dramatically
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*-------------------------------------------------------------------------------*/
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esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
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{
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if (!out_size_bytes) {
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return ESP_ERR_INVALID_ARG;
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}
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*out_size_bytes = s_psram_size;
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return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
|
|
}
|
|
|
|
/**
|
|
* This function is to get the available physical psram size in bytes.
|
|
*
|
|
* When ECC is enabled, the available size will be reduced.
|
|
* On S3 Quad PSRAM, ECC is not enabled for now.
|
|
*/
|
|
esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
|
|
{
|
|
if (!out_size_bytes) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
|
|
*out_size_bytes = s_psram_size;
|
|
return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
|
|
}
|