kopia lustrzana https://github.com/espressif/esp-idf
197 wiersze
7.3 KiB
C
197 wiersze
7.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_private/esp_clk_tree_common.h"
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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#include "soc/rtc.h"
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#include "esp_private/esp_clk.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/soc_caps.h"
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#include "sdkconfig.h"
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#include "esp_hw_log.h"
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static const char *TAG = "esp_clk_tree_common";
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typedef struct esp_clk_tree_calibrated_freq_t esp_clk_tree_calibrated_freq_t;
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struct esp_clk_tree_calibrated_freq_t {
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#if SOC_CLK_RC_FAST_D256_SUPPORTED
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uint32_t rc_fast_d256;
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#elif SOC_CLK_RC_FAST_SUPPORT_CALIBRATION // && !SOC_CLK_RC_FAST_D256_SUPPORTED
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uint32_t rc_fast;
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#endif
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#if SOC_CLK_XTAL32K_SUPPORTED
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uint32_t xtal32k;
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#endif
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#if SOC_CLK_OSC_SLOW_SUPPORTED
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uint32_t osc_slow;
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#endif
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};
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// TODO: Better to implement a spinlock for the static variables
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static esp_clk_tree_calibrated_freq_t s_calibrated_freq = {};
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/* Number of cycles for RTC_SLOW_CLK calibration */
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#define RTC_SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
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/* Number of cycles for ~32kHz clocks calibration (rc_fast_d256, xtal32k, osc_slow, rc32k) */
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#define DEFAULT_32K_CLK_CAL_CYCLES 100
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/* Number of cycles for RC_FAST calibration */
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#define DEFAULT_RC_FAST_CAL_CYCLES 10000 // RC_FAST has a higher frequency, therefore, requires more cycles to get an accurate value
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/**
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* Performs a frequency calibration to RTC slow clock
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*
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* slowclk_cycles Number of slow clock cycles to count.
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* If slowclk_cycles = 0, calibration will not be performed. Clock's theoretical value will be used.
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*
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* Returns the number of XTAL clock cycles within the given number of slow clock cycles
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* It returns 0 if calibration failed, i.e. clock is not running
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*/
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static uint32_t clk_tree_rtc_slow_calibration(uint32_t slowclk_cycles)
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{
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uint32_t cal_val = 0;
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if (slowclk_cycles > 0) {
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cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, slowclk_cycles);
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} else {
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const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
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uint32_t source_approx_freq = clk_hal_lp_slow_get_freq_hz();
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assert(source_approx_freq);
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cal_val = (uint32_t)(cal_dividend / source_approx_freq);
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}
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if (cal_val) {
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ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
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// Update the calibration value of RTC_SLOW_CLK
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esp_clk_slowclk_cal_set(cal_val);
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}
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return cal_val;
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}
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#if SOC_CLK_RC_FAST_D256_SUPPORTED
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uint32_t esp_clk_tree_rc_fast_d256_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
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{
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switch (precision) {
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX:
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return SOC_CLK_RC_FAST_D256_FREQ_APPROX;
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
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if (!s_calibrated_freq.rc_fast_d256) {
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s_calibrated_freq.rc_fast_d256 = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, DEFAULT_32K_CLK_CAL_CYCLES));
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}
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return s_calibrated_freq.rc_fast_d256;
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
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s_calibrated_freq.rc_fast_d256 = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, DEFAULT_32K_CLK_CAL_CYCLES));
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return s_calibrated_freq.rc_fast_d256;
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default:
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return 0;
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}
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}
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#endif
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#if SOC_CLK_XTAL32K_SUPPORTED
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uint32_t esp_clk_tree_xtal32k_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
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{
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switch (precision) {
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX:
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return SOC_CLK_XTAL32K_FREQ_APPROX;
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
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if (!s_calibrated_freq.xtal32k) {
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s_calibrated_freq.xtal32k = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_XTAL, DEFAULT_32K_CLK_CAL_CYCLES));
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}
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return s_calibrated_freq.xtal32k;
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
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s_calibrated_freq.xtal32k = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_XTAL, DEFAULT_32K_CLK_CAL_CYCLES));
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return s_calibrated_freq.xtal32k;
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default:
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return 0;
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}
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}
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#endif
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#if SOC_CLK_OSC_SLOW_SUPPORTED
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uint32_t esp_clk_tree_osc_slow_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
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{
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switch (precision) {
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX:
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return SOC_CLK_OSC_SLOW_FREQ_APPROX;
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
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if (!s_calibrated_freq.osc_slow) {
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s_calibrated_freq.osc_slow = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_OSC_SLOW, DEFAULT_32K_CLK_CAL_CYCLES));
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}
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return s_calibrated_freq.osc_slow;
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
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s_calibrated_freq.osc_slow = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_32K_OSC_SLOW, DEFAULT_32K_CLK_CAL_CYCLES));
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return s_calibrated_freq.osc_slow;
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default:
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return 0;
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}
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}
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#endif
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uint32_t esp_clk_tree_lp_slow_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
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{
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switch (precision) {
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED:
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// This returns calibrated (if CONFIG_xxx_RTC_CLK_CAL_CYCLES) value stored in RTC storage register
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return rtc_clk_freq_cal(clk_ll_rtc_slow_load_cal());
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX:
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return clk_hal_lp_slow_get_freq_hz();
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case ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT:
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return rtc_clk_freq_cal(clk_tree_rtc_slow_calibration(RTC_SLOW_CLK_CAL_CYCLES));
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default:
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return 0;
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}
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}
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uint32_t esp_clk_tree_rc_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
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{
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#if SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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if (precision == ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX) {
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return SOC_CLK_RC_FAST_FREQ_APPROX;
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}
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#if SOC_CLK_RC_FAST_D256_SUPPORTED
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// If RC_FAST_D256 clock exists, calibration on a slow freq clock is much faster (less slow clock cycles need to wait)
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return esp_clk_tree_rc_fast_d256_get_freq_hz(precision) << 8;
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#else
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// Calibrate directly on the RC_FAST clock requires much more slow clock cycles to get an accurate freq value
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if (precision != ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED || !s_calibrated_freq.rc_fast) {
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s_calibrated_freq.rc_fast = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_RC_FAST, DEFAULT_RC_FAST_CAL_CYCLES));
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}
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return s_calibrated_freq.rc_fast;
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#endif //SOC_CLK_RC_FAST_D256_SUPPORTED
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#else //!SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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if (precision != ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX) {
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// No way of getting exact rc_fast freq
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ESP_HW_LOGW(TAG, "unable to get the exact freq of rc_fast_clk, returning its approx. freq value");
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}
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return SOC_CLK_RC_FAST_FREQ_APPROX;
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#endif //SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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}
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uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
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{
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switch (clk_ll_rtc_fast_get_src()) {
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case SOC_RTC_FAST_CLK_SRC_XTAL_DIV:
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 //SOC_RTC_FAST_CLK_SRC_XTAL_D4
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return clk_hal_xtal_get_freq_mhz() * MHZ >> 2;
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#elif CONFIG_IDF_TARGET_ESP32P4 //SOC_RTC_FAST_CLK_SRC_XTAL
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return clk_hal_xtal_get_freq_mhz() * MHZ;
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#else //SOC_RTC_FAST_CLK_SRC_XTAL_D2
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return clk_hal_xtal_get_freq_mhz() * MHZ >> 1;
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#endif
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case SOC_RTC_FAST_CLK_SRC_RC_FAST:
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return esp_clk_tree_rc_fast_get_freq_hz(precision) / clk_ll_rc_fast_get_divider();
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#if SOC_CLK_LP_FAST_SUPPORT_LP_PLL
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case SOC_RTC_FAST_CLK_SRC_LP_PLL:
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return clk_ll_lp_pll_get_freq_mhz() * MHZ;
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#endif
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default:
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// Invalid clock source
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assert(false);
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return 0;
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}
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}
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