kopia lustrzana https://github.com/espressif/esp-idf
39 wiersze
1.4 KiB
C
39 wiersze
1.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "esp_log.h"
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#include "soc/soc_caps.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/mspi_timing_config.h"
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#include "mspi_timing_tuning_configs.h"
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#include "hal/psram_ctrlr_ll.h"
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const static char *TAG = "MSPI Timing";
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//-------------------------------------MSPI Clock Setting-------------------------------------//
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void mspi_timing_config_set_psram_clock(uint32_t psram_freq_mhz, mspi_timing_speed_mode_t speed_mode, bool control_both_mspi)
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{
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uint32_t freqdiv = MSPI_TIMING_MPLL_FREQ_MHZ / MSPI_TIMING_CORE_CLOCK_DIV / psram_freq_mhz;
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assert(freqdiv > 0);
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ESP_EARLY_LOGD(TAG, "psram_freq_mhz: %" PRIu32 " mhz, bus clock div: %" PRIu32, psram_freq_mhz, freqdiv);
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PERIPH_RCC_ATOMIC() {
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//MSPI2 and MSPI3 share the register for core clock. So we only set MSPI2 here.
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psram_ctrlr_ll_set_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, MSPI_TIMING_CORE_CLOCK_DIV);
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psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_3, freqdiv);
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psram_ctrlr_ll_set_bus_clock(PSRAM_CTRLR_LL_MSPI_ID_2, freqdiv);
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}
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}
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void mspi_timing_config_set_flash_clock(uint32_t flash_freq_mhz, mspi_timing_speed_mode_t speed_mode, bool control_both_mspi)
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{
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//For compatibility
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}
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