kopia lustrzana https://github.com/espressif/esp-idf
224 wiersze
11 KiB
C
224 wiersze
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_log.h"
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#include "assert.h"
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#include "esp_efuse_utility.h"
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#include "soc/efuse_periph.h"
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#include "hal/efuse_hal.h"
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static const char *TAG = "efuse";
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#ifdef CONFIG_EFUSE_VIRTUAL
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extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
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#endif // CONFIG_EFUSE_VIRTUAL
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/*Range addresses to read blocks*/
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const esp_efuse_range_addr_t range_read_addr_blocks[] = {
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{EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
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{EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
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{EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
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{EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
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{EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
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{EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
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{EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2
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{EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
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{EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
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{EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
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{EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6
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};
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static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
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/*Range addresses to write blocks (it is not real regs, it is buffer) */
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const esp_efuse_range_addr_t range_write_addr_blocks[] = {
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{(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
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{(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
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{(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
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{(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
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{(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
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{(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
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{(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
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{(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
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{(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
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{(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
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{(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
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};
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#ifndef CONFIG_EFUSE_VIRTUAL
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// Update Efuse timing configuration
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static esp_err_t esp_efuse_set_timing(void)
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{
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// efuse clock is fixed.
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// An argument (0) is for compatibility and will be ignored.
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efuse_hal_set_timing(0);
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return ESP_OK;
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}
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#endif // ifndef CONFIG_EFUSE_VIRTUAL
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// Efuse read operation: copies data from physical efuses to efuse read registers.
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void esp_efuse_utility_clear_program_registers(void)
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{
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efuse_hal_read();
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efuse_hal_clear_program_registers();
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}
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esp_err_t esp_efuse_utility_check_errors(void)
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{
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if (efuse_ll_get_err_rst_enable()) {
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for (unsigned i = 0; i < 5; i++) {
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uint32_t error_reg = REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4);
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if (error_reg) {
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uint32_t data_reg = REG_READ(EFUSE_RD_REPEAT_DATA0_REG + i * 4);
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if (error_reg & data_reg) {
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// For 0001 situation (4x coding scheme):
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// an error bit points that data bit is wrong in case the data bit equals 1. (need to reboot in this case).
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ESP_EARLY_LOGE(TAG, "Error in EFUSE_RD_REPEAT_DATA%d_REG of BLOCK0 (error_reg=0x%08" PRIx32 ", data_reg=0x%08" PRIx32 "). Need to reboot", i, error_reg, data_reg);
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efuse_hal_read();
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return ESP_FAIL;
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}
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}
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}
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}
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return ESP_OK;
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}
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// Burn values written to the efuse write registers
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esp_err_t esp_efuse_utility_burn_chip(void)
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{
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return esp_efuse_utility_burn_chip_opt(false, true);
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}
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esp_err_t esp_efuse_utility_burn_chip_opt(bool ignore_coding_errors, bool verify_written_data)
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{
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esp_err_t error = ESP_OK;
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#ifdef CONFIG_EFUSE_VIRTUAL
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(void) ignore_coding_errors;
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(void) verify_written_data;
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ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
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for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
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int subblock = 0;
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
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virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
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}
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}
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#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
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esp_efuse_utility_write_efuses_to_flash();
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#endif
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#else // CONFIG_EFUSE_VIRTUAL
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if (esp_efuse_set_timing() != ESP_OK) {
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ESP_LOGE(TAG, "Efuse fields are not burnt");
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} else {
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// Permanently update values written to the efuse write registers
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// It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
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for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
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bool need_burn_block = false;
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
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if (REG_READ(addr_wr_block) != 0) {
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need_burn_block = true;
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break;
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}
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}
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if (!need_burn_block) {
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continue;
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}
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if (error) {
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// It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data)
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// in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2.
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ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block);
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continue;
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}
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efuse_hal_clear_program_registers();
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if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
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uint8_t block_rs[12];
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efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
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hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
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}
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unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t);
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unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
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memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
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uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data
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hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data));
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int repeat_burn_op = 1;
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bool correct_written_data;
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bool coding_error_before = !ignore_coding_errors && efuse_hal_is_coding_error_in_block(num_block);
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if (coding_error_before) {
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ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block);
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}
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bool coding_error_occurred;
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do {
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ESP_LOGI(TAG, "BURN BLOCK%d", num_block);
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efuse_hal_program(num_block); // BURN a block
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bool coding_error_after;
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for (unsigned i = 0; i < 5; i++) {
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efuse_hal_read();
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coding_error_after = efuse_hal_is_coding_error_in_block(num_block);
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if (coding_error_after == true) {
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break;
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}
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}
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coding_error_occurred = !ignore_coding_errors && (coding_error_before != coding_error_after) && !coding_error_before;
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if (coding_error_occurred) {
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ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block);
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}
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correct_written_data = (verify_written_data) ? esp_efuse_utility_is_correct_written_data(num_block, r_data_len) : true;
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if (!correct_written_data || coding_error_occurred) {
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ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op);
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hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data));
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}
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} while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3);
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if (coding_error_occurred) {
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ESP_LOGW(TAG, "Coding error was not fixed");
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if (num_block == 0) {
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ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security");
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error = ESP_FAIL;
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}
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}
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if (!correct_written_data) {
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ESP_LOGE(TAG, "Written data are incorrect");
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error = ESP_FAIL;
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}
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}
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}
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#endif // CONFIG_EFUSE_VIRTUAL
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esp_efuse_utility_reset();
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return error;
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}
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// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
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// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
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// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
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// They will be filled during the burn operation.
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esp_err_t esp_efuse_utility_apply_new_coding_scheme()
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{
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// start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
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for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
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if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
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if (REG_READ(addr_wr_block)) {
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int num_reg = 0;
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for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
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if (esp_efuse_utility_read_reg(num_block, num_reg)) {
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ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
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return ESP_ERR_CODING;
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}
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}
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break;
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}
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}
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}
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}
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return ESP_OK;
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}
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