kopia lustrzana https://github.com/espressif/esp-idf
398 wiersze
19 KiB
Plaintext
398 wiersze
19 KiB
Plaintext
config SPIRAM
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bool "Support for external, SPI-connected RAM"
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default "n"
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help
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This enables support for an external SPI RAM chip, connected in parallel with the
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main SPI flash chip.
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menu "SPI RAM config"
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depends on SPIRAM
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config SPIRAM_MODE_QUAD
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bool
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default "y"
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choice SPIRAM_TYPE
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prompt "Type of SPI RAM chip in use"
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default SPIRAM_TYPE_AUTO
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config SPIRAM_TYPE_AUTO
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bool "Auto-detect"
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config SPIRAM_TYPE_ESPPSRAM16
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bool "ESP-PSRAM16 or APS1604"
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config SPIRAM_TYPE_ESPPSRAM32
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bool "ESP-PSRAM32"
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config SPIRAM_TYPE_ESPPSRAM64
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bool "ESP-PSRAM64 or LY68L6400"
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endchoice
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choice SPIRAM_SPEED
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prompt "Set RAM clock speed"
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default SPIRAM_SPEED_40M
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help
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Select the speed for the SPI RAM chip.
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If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
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1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz
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2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz
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3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz
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Note: If the third mode(80Mhz+80Mhz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
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will be occupied by the system. Which SPI host to use can be selected by the config item
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SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
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option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
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(ESPTOOLPY_FLASHFREQ_80M is true)
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config SPIRAM_SPEED_40M
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bool "40MHz clock speed"
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config SPIRAM_SPEED_80M
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depends on ESPTOOLPY_FLASHFREQ_80M
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bool "80MHz clock speed"
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endchoice
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config SPIRAM_SPEED
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int
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default 80 if SPIRAM_SPEED_80M
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default 40 if SPIRAM_SPEED_40M
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source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common" # insert non-chip-specific items here
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config SPIRAM_CACHE_WORKAROUND
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bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
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depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN < 3)
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default "y"
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help
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Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations
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when the cache line needs to be fetched from external RAM and an interrupt occurs. This enables a
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fix in the compiler (-mfix-esp32-psram-cache-issue) that makes sure the specific code that is
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vulnerable to this will not be emitted.
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This will also not use any bits of newlib that are located in ROM, opting for a version that is
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compiled with the workaround and located in flash instead.
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The workaround is not required for ESP32 revision 3 and above.
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menu "SPIRAM cache workaround debugging"
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choice SPIRAM_CACHE_WORKAROUND_STRATEGY
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prompt "Workaround strategy"
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depends on SPIRAM_CACHE_WORKAROUND
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default SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
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help
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Select the workaround strategy. Note that the strategy for precompiled
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libraries (libgcc, newlib, bt, wifi) is not affected by this selection.
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Unless you know you need a different strategy, it's suggested you stay
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with the default MEMW strategy. Note that DUPLDST can interfere with hardware
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encryption and this will be automatically disabled if this workaround is selected.
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'Insert nops' is the workaround that was used in older esp-idf versions. This workaround
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still can cause faulty data transfers from/to SPI RAM in some situation.
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config SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
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bool "Insert memw after vulnerable instructions (default)"
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config SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
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bool "Duplicate LD/ST for 32-bit, memw for 8/16 bit"
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config SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS
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bool "Insert nops between vulnerable loads/stores (old strategy, obsolete)"
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endchoice
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#This needs to be Y only for the dupldst workaround
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config SPIRAM_WORKAROUND_NEED_VOLATILE_SPINLOCK
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bool
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default "y" if SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
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endmenu
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menu "SPIRAM workaround libraries placement"
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visible if SPIRAM_CACHE_WORKAROUND
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config SPIRAM_CACHE_LIBJMP_IN_IRAM
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bool "Put libc's jump related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: longjmp and setjmp.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBMATH_IN_IRAM
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bool "Put libc's math related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: abs, div, labs, ldiv, quorem, fpclassify,
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and nan.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBNUMPARSER_IN_IRAM
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bool "Put libc's number parsing related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: utoa, itoa, atoi, atol, strtol, and strtoul.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBIO_IN_IRAM
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bool "Put libc's I/O related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: wcrtomb, fvwrite, wbuf, wsetup, fputwc, wctomb_r,
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ungetc, makebuf, fflush, refill, and sccl.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBTIME_IN_IRAM
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bool "Put libc's time related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: asctime, asctime_r, ctime, ctime_r, lcltime, lcltime_r,
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gmtime, gmtime_r, strftime, mktime, tzset_r, tzset, time, gettzinfo, systimes, month_lengths,
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timelocal, tzvars, tzlock, tzcalc_limits, and strptime.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBCHAR_IN_IRAM
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bool "Put libc's characters related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: ctype_, toupper, tolower, toascii, strupr, bzero,
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isalnum, isalpha, isascii, isblank, iscntrl, isdigit, isgraph, islower, isprint, ispunct,
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isspace, and isupper.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBMEM_IN_IRAM
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bool "Put libc's memory related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: memccpy, memchr memmove, and memrchr.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBSTR_IN_IRAM
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bool "Put libc's string related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: strcasecmp, strcasestr, strchr, strcoll,
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strcpy, strcspn, strdup, strdup_r, strlcat, strlcpy, strlen, strlwr, strncasecmp,
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strncat, strncmp, strncpy, strndup, strndup_r, strrchr, strsep, strspn, strstr,
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strtok_r, and strupr.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBRAND_IN_IRAM
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bool "Put libc's random related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: srand, rand, and rand_r.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBENV_IN_IRAM
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bool "Put libc's environment related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: environ, envlock, and getenv_r.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBFILE_IN_IRAM
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bool "Put libc's file related functions in IRAM"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: lock, isatty, fclose, open, close, creat, read,
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rshift, sbrk, stdio, syssbrk, sysclose, sysopen, creat, sysread, syswrite, impure, fwalk,
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and findfp.
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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config SPIRAM_CACHE_LIBMISC_IN_IRAM
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bool "Put libc's miscellaneous functions in IRAM, see help"
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depends on SPIRAM_CACHE_WORKAROUND
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default "y"
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help
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The functions affected by this option are: raise and system
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Putting these function in IRAM will allow them to be called when flash cache is disabled
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but it will also reduce the available size of free IRAM for the user application.
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endmenu
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config SPIRAM_BANKSWITCH_ENABLE
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bool "Enable bank switching for >4MiB external RAM"
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default y
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depends on SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
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help
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The ESP32 only supports 4MiB of external RAM in its address space. The hardware does support larger
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memories, but these have to be bank-switched in and out of this address space. Enabling this allows you
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to reserve some MMU pages for this, which allows the use of the esp_himem api to manage these banks.
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#Note that this is limited to 62 banks, as esp_psram_extram_writeback_cache needs some kind of mapping of
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#some banks below that mark to work. We cannot at this moment guarantee this to exist when himem is
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#enabled.
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If spiram 2T mode is enabled, the size of 64Mbit psram will be changed as 32Mbit, so himem will be
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unusable.
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config SPIRAM_BANKSWITCH_RESERVE
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int "Amount of 32K pages to reserve for bank switching"
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depends on SPIRAM_BANKSWITCH_ENABLE
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default 8
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range 1 62
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help
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Select the amount of banks reserved for bank switching. Note that the amount of RAM allocatable with
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malloc/esp_heap_alloc_caps will decrease by 32K for each page reserved here.
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Note that this reservation is only actually done if your program actually uses the himem API. Without
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any himem calls, the reservation is not done and the original amount of memory will be available
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to malloc/esp_heap_alloc_caps.
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config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
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bool "Allow external memory as an argument to xTaskCreateStatic"
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default n
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depends on SPIRAM_USE_MALLOC
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help
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Because some bits of the ESP32 code environment cannot be recompiled with the cache workaround,
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normally tasks cannot be safely run with their stack residing in external memory; for this reason
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xTaskCreate (and related task creaton functions) always allocate stack in internal memory and
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xTaskCreateStatic will check if the memory passed to it is in internal memory. If you have a task that
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needs a large amount of stack and does not call on ROM code in any way (no direct calls, but also no
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Bluetooth/WiFi), you can try enable this to cause xTaskCreateStatic to allow tasks stack in external
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memory.
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choice SPIRAM_OCCUPY_SPI_HOST
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prompt "SPI host to use for 32MBit PSRAM"
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default SPIRAM_OCCUPY_VSPI_HOST
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depends on SPIRAM_SPEED_80M
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help
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When both flash and PSRAM is working under 80MHz, and the PSRAM is of type 32MBit, one of the HSPI/VSPI
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host will be used to output the clock. Select which one to use here.
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config SPIRAM_OCCUPY_HSPI_HOST
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bool "HSPI host (SPI2)"
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config SPIRAM_OCCUPY_VSPI_HOST
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bool "VSPI host (SPI3)"
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config SPIRAM_OCCUPY_NO_HOST
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bool "Will not try to use any host, will abort if not able to use the PSRAM"
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endchoice
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menu "PSRAM clock and cs IO for ESP32-DOWD"
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config D0WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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depends on SPIRAM
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range 0 33
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default 17
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help
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The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
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1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D0WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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depends on SPIRAM
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range 0 33
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default 16
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
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1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-D2WD"
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config D2WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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depends on SPIRAM
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range 0 33
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default 9
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help
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User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
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so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D2WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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depends on SPIRAM
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range 0 33
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default 10
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help
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User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
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so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-PICO"
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config PICO_PSRAM_CS_IO
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int "PSRAM CS IO number"
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depends on SPIRAM
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range 0 33
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default 10
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
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For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
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IO.
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For the reference hardware design, please refer to
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https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
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endmenu
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config SPIRAM_CUSTOM_SPIWP_SD3_PIN
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bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
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depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT)
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default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5
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default n
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help
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This setting is only used if the SPI flash pins have been overridden by setting the eFuses
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SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
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When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
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ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
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mode, so a WP pin setting is necessary.
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If this config item is set to N (default), the correct WP pin will be automatically used for any
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Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
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to Y and specify the GPIO number connected to the WP pin.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
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configured in the bootloader.
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config SPIRAM_SPIWP_SD3_PIN
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int "Custom SPI PSRAM WP(SD3) Pin"
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depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT)
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#depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN # backwards compatibility, can uncomment in IDF 5
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range 0 33
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default 7
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help
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The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
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If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
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value to the GPIO number of the SPIRAM WP pin.
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config SPIRAM_2T_MODE
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bool "Enable SPI PSRAM 2T mode"
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depends on SPIRAM
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default "n"
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help
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Enable this option to fix single bit errors inside 64Mbit PSRAM.
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Some 64Mbit PSRAM chips have a hardware issue in the RAM which causes bit errors at multiple
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fixed bit positions.
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Note: If this option is enabled, the 64Mbit PSRAM chip will appear to be 32Mbit in size.
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Applications will not be affected unless the use the esp_himem APIs, which are not supported
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in 2T mode.
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endmenu # "SPI RAM config"
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