kopia lustrzana https://github.com/espressif/esp-idf
681 wiersze
20 KiB
C
681 wiersze
20 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use in application code.
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* See readme.md in hal/include/hal/readme.md
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******************************************************************************/
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// The LL layer for ESP32-C61 GPIO register operations
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#pragma once
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#include <stdlib.h>
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#include <stdbool.h>
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#include "soc/soc.h"
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#include "soc/gpio_periph.h"
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#include "soc/gpio_struct.h"
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#include "soc/lp_aon_struct.h"
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#include "soc/lp_gpio_struct.h"
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#include "soc/pmu_struct.h"
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#include "soc/usb_serial_jtag_reg.h"
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#include "soc/pcr_struct.h"
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#include "soc/clk_tree_defs.h"
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#include "hal/gpio_types.h"
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#include "hal/misc.h"
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#include "hal/assert.h"
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// TODO: [ESP32C61] IDF-9316, inherit from c6
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Get GPIO hardware instance with giving gpio num
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#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
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#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0))
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#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1))
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/**
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* @brief Get the configuration for an IO
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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* @param pu Pull-up enabled or not
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* @param pd Pull-down enabled or not
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* @param ie Input enabled or not
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* @param oe Output enabled or not
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* @param od Open-drain enabled or not
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* @param drv Drive strength value
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* @param fun_sel IOMUX function selection value
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* @param sig_out Outputting peripheral signal index
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* @param slp_sel Pin sleep mode enabled or not
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*/
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static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
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bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
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uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
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{
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uint32_t bit_mask = 1 << gpio_num;
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uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
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*pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
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*pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
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*ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
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*oe = (hw->enable.val & bit_mask) >> gpio_num;
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*od = hw->pinn[gpio_num].pinn_pad_driver;
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*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
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*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
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*sig_out = hw->funcn_out_sel_cfg[gpio_num].funcn_out_sel;
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*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
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}
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/**
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* @brief Enable pull-up on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
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{
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REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
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}
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/**
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* @brief Disable pull-up on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
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{
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REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
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}
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/**
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* @brief Enable pull-down on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
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{
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REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
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}
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/**
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* @brief Disable pull-down on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
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{
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// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
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// USB DP pin is default to PU enabled
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// Note that esp32c61 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
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// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
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// TODO: read the specific efuse with efuse_ll.h
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// if (gpio_num == USB_DP_GPIO_NUM) {
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// SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
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// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
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// }
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REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
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}
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/**
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* @brief GPIO set interrupt trigger type
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16);
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* @param intr_type Interrupt type, select from gpio_int_type_t
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*/
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static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type)
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{
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hw->pinn[gpio_num].pinn_int_type = intr_type;
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}
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/**
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* @brief Get GPIO interrupt status
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param core_id interrupt core id
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* @param status interrupt status
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
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{
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(void)core_id;
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*status = hw->procpu_int.procpu_int;
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}
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/**
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* @brief Get GPIO interrupt status high
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param core_id interrupt core id
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* @param status interrupt status high
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
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{
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*status = 0; // Less than 32 GPIOs in ESP32-C61
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}
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/**
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* @brief Clear GPIO interrupt status
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param mask interrupt status clear mask
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
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{
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hw->status_w1tc.status_w1tc = mask;
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}
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/**
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* @brief Clear GPIO interrupt status high
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param mask interrupt status high clear mask
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
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{
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// Less than 32 GPIOs on ESP32-C61 Do nothing.
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}
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/**
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* @brief Enable GPIO module interrupt signal
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param core_id Interrupt enabled CPU to corresponding ID
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* @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
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{
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HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
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GPIO.pinn[gpio_num].pinn_int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr
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}
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/**
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* @brief Disable GPIO module interrupt signal
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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hw->pinn[gpio_num].pinn_int_ena = 0; //disable GPIO intr
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}
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/**
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* @brief Disable input mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
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}
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/**
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* @brief Enable input mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
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}
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/**
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* @brief Enable GPIO pin filter
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number of the pad.
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*/
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static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4));
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}
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/**
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* @brief Disable GPIO pin filter
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number of the pad.
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*/
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static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
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}
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/**
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* @brief Disable output mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num);
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// Ensure no other output signal is routed via GPIO matrix to this pin
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REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), SIG_GPIO_OUT_IDX);
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}
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/**
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* @brief Enable output mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
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}
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/**
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* @brief Disable open-drain mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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hw->pinn[gpio_num].pinn_pad_driver = 0;
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}
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/**
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* @brief Enable open-drain mode on GPIO.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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hw->pinn[gpio_num].pinn_pad_driver = 1;
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}
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/**
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* @brief GPIO set output level
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
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* @param level Output level. 0: low ; 1: high
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
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{
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if (level) {
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hw->out_w1ts.out_w1ts = (1 << gpio_num);
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} else {
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hw->out_w1tc.out_w1tc = (1 << gpio_num);
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}
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}
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/**
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* @brief GPIO get input level
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*
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* @warning If the pad is not configured for input (or input and output) the returned value is always 0.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
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*
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* @return
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* - 0 the GPIO input level is 0
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* - 1 the GPIO input level is 1
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*/
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static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
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{
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return (hw->in.in_data_next >> gpio_num) & 0x1;
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}
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/**
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* @brief Enable GPIO wake-up function.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number.
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*/
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static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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hw->pinn[gpio_num].pinn_wakeup_enable = 0x1;
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}
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/**
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* @brief Disable GPIO wake-up function.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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hw->pinn[gpio_num].pinn_wakeup_enable = 0;
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}
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/**
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* @brief Set GPIO pad drive capability
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number, only support output GPIOs
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* @param strength Drive capability of the pad
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*/
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static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
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{
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SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
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}
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/**
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* @brief Get GPIO pad drive capability
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number, only support output GPIOs
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* @param strength Pointer to accept drive capability of the pad
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*/
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static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
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{
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*strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
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}
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/**
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* @brief Enable gpio pad hold function.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number, only support output GPIOs
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*/
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static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
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{
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LP_AON.gpio_hold0.gpio_hold0 |= GPIO_HOLD_MASK[gpio_num];
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}
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/**
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* @brief Disable gpio pad hold function.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number, only support output GPIOs
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*/
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static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
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{
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LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num];
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}
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/**
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* @brief Get digital gpio pad hold status.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number, only support output GPIOs
|
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*
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* @note caller must ensure that gpio_num is a digital io pad
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*
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* @return
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* - true digital gpio pad is held
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* - false digital gpio pad is unheld
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*/
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__attribute__((always_inline))
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static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
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{
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return !!(LP_AON.gpio_hold0.gpio_hold0 & BIT(gpio_num));
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}
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/**
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* @brief Set pad input to a peripheral signal through the IOMUX.
|
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number of the pad.
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* @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``.
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*/
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__attribute__((always_inline))
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static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
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{
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REG_CLR_BIT(GPIO_FUNC0_IN_SEL_CFG_REG + signal_idx * 4, GPIO_SIG0_IN_SEL);
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PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4));
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}
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|
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/**
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* @brief Select a function for the pin in the IOMUX
|
||
*
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* @param pin_name Pin name to configure
|
||
* @param func Function to assign to the pin
|
||
*/
|
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static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
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{
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// Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
|
||
if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) {
|
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CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
|
||
}
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PIN_FUNC_SELECT(pin_name, func);
|
||
}
|
||
|
||
/**
|
||
* @brief Control the pin in the IOMUX
|
||
*
|
||
* @param bmap write mask of control value
|
||
* @param val Control value
|
||
* @param shift write mask shift of control value
|
||
*/
|
||
static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
|
||
{
|
||
SET_PERI_REG_BITS(PIN_CTRL, bmap, val, shift);
|
||
}
|
||
|
||
/**
|
||
* @brief Select a function for the pin in the IOMUX
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
* @param func Function to assign to the pin
|
||
*/
|
||
__attribute__((always_inline))
|
||
static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
|
||
{
|
||
// Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
|
||
// if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) {
|
||
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
|
||
// }
|
||
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
|
||
}
|
||
|
||
/**
|
||
* @brief Set peripheral output to an GPIO pad through the IOMUX.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num gpio_num GPIO number of the pad.
|
||
* @param func The function number of the peripheral pin to output pin.
|
||
* One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``.
|
||
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
|
||
*/
|
||
static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
|
||
{
|
||
hw->funcn_out_sel_cfg[gpio_num].funcn_oe_sel = 0;
|
||
hw->funcn_out_sel_cfg[gpio_num].funcn_oe_inv_sel = oen_inv;
|
||
gpio_ll_func_sel(hw, gpio_num, func);
|
||
}
|
||
|
||
/**
|
||
* @brief Set clock source of IO MUX module
|
||
*
|
||
* @param src IO MUX clock source (only a subset of soc_module_clk_t values are valid)
|
||
*/
|
||
static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
|
||
{
|
||
switch (src) {
|
||
case SOC_MOD_CLK_XTAL:
|
||
PCR.iomux_clk_conf.iomux_func_clk_sel = 3;
|
||
break;
|
||
case SOC_MOD_CLK_PLL_F80M:
|
||
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
|
||
break;
|
||
default:
|
||
// Unsupported IO_MUX clock source
|
||
HAL_ASSERT(false);
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Get the GPIO number that is routed to the input peripheral signal through GPIO matrix.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param in_sig_idx Peripheral signal index (tagged as input attribute).
|
||
*
|
||
* @return
|
||
* - -1 Signal bypassed GPIO matrix
|
||
* - Others GPIO number
|
||
*/
|
||
static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx)
|
||
{
|
||
uint32_t reg_val = REG_READ(GPIO_FUNC0_IN_SEL_CFG_REG + in_sig_idx * 4);
|
||
if (reg_val & GPIO_SIG0_IN_SEL) {
|
||
return (reg_val & GPIO_FUNC0_IN_SEL_M);
|
||
} else {
|
||
return -1;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Force hold digital io pad.
|
||
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
|
||
*/
|
||
static inline void gpio_ll_force_hold_all(void)
|
||
{
|
||
// WT flag, it gets self-cleared after the configuration is done
|
||
PMU.imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
|
||
}
|
||
|
||
/**
|
||
* @brief Force unhold digital io pad.
|
||
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
|
||
*/
|
||
static inline void gpio_ll_force_unhold_all(void)
|
||
{
|
||
// WT flag, it gets self-cleared after the configuration is done
|
||
PMU.imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
|
||
}
|
||
|
||
/**
|
||
* @brief Enable GPIO pin to use sleep mode pin functions during light sleep.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
*/
|
||
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
|
||
{
|
||
PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
|
||
}
|
||
|
||
/**
|
||
* @brief Disable GPIO pin to use sleep mode pin functions during light sleep.
|
||
* Pin functions remains the same in both normal execution and in light-sleep mode.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
*/
|
||
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
|
||
{
|
||
PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
|
||
}
|
||
|
||
/**
|
||
* @brief Disable GPIO pull-up in sleep mode.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
*/
|
||
static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
|
||
{
|
||
PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
|
||
}
|
||
|
||
/**
|
||
* @brief Enable GPIO pull-up in sleep mode.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
*/
|
||
static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
|
||
{
|
||
PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
|
||
}
|
||
|
||
/**
|
||
* @brief Enable GPIO pull-down in sleep mode.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
*/
|
||
static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
|
||
{
|
||
PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
|
||
}
|
||
|
||
/**
|
||
* @brief Disable GPIO pull-down in sleep mode.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
*/
|
||
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
|
||
{
|
||
PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
|
||
}
|
||
|
||
/**
|
||
* @brief Disable GPIO input in sleep mode.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
*/
|
||
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
|
||
{
|
||
PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
|
||
}
|
||
|
||
/**
|
||
* @brief Enable GPIO input in sleep mode.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
*/
|
||
static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
|
||
{
|
||
PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
|
||
}
|
||
|
||
/**
|
||
* @brief Disable GPIO output in sleep mode.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
*/
|
||
static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
|
||
{
|
||
PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
|
||
}
|
||
|
||
/**
|
||
* @brief Enable GPIO output in sleep mode.
|
||
*
|
||
* @param hw Peripheral GPIO hardware instance address.
|
||
* @param gpio_num GPIO number
|
||
*/
|
||
static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
|
||
{
|
||
PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
|
||
}
|
||
|
||
#ifdef __cplusplus
|
||
}
|
||
#endif
|