kopia lustrzana https://github.com/espressif/esp-idf
159 wiersze
6.4 KiB
C
159 wiersze
6.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "unity.h"
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#include "driver/gpio.h"
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#include "esp_err.h"
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#include "esp_clock_output.h"
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#include "hal/gpio_hal.h"
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#include "soc/rtc.h"
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#define TEST_LOOPS 100
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#if CONFIG_IDF_TARGET_ESP32
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static const int test_clk_out_io[] = {0, 1, 3};
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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static const int test_clk_out_io[] = {18, 19, 20};
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#elif CONFIG_IDF_TARGET_ESP32P4
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static const int test_clk_out_io[] = {7, 8};
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#else
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static const int test_clk_out_io[] = {3, 4, 5, 6};
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#endif
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static soc_clkout_sig_id_t test_clk_out_sig[] = {CLKOUT_SIG_XTAL, CLKOUT_SIG_RC_SLOW, CLKOUT_SIG_RC_FAST, CLKOUT_SIG_INVALID};
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static SemaphoreHandle_t test_done_semphr;
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void output_clock_1(void *pvParameter)
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{
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esp_clock_output_mapping_handle_t clkout_mapping_hdl;
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for (int i = 0; i < TEST_LOOPS; ++i) {
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TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[0], test_clk_out_io[0], &clkout_mapping_hdl));
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vTaskDelay(3);
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TEST_ESP_OK(esp_clock_output_stop(clkout_mapping_hdl));
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vTaskDelay(7);
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}
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xSemaphoreGive(test_done_semphr);
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vTaskDelete(NULL);
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}
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void output_clock_2(void *pvParameter)
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{
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esp_clock_output_mapping_handle_t clkout_mapping_hdl;
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for (int i = 0; i < TEST_LOOPS; ++i) {
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TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[1], test_clk_out_io[1], &clkout_mapping_hdl));
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vTaskDelay(4);
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TEST_ESP_OK(esp_clock_output_stop(clkout_mapping_hdl));
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vTaskDelay(6);
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}
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xSemaphoreGive(test_done_semphr);
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vTaskDelete(NULL);
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}
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#if SOC_GPIO_CLOCKOUT_CHANNEL_NUM >= 3
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void output_clock_3(void *pvParameter)
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{
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rtc_dig_clk8m_enable();
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esp_clock_output_mapping_handle_t clkout_mapping_hdl;
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for (int i = 0; i < TEST_LOOPS; ++i) {
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TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[2], test_clk_out_io[2], &clkout_mapping_hdl));
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vTaskDelay(5);
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TEST_ESP_OK(esp_clock_output_stop(clkout_mapping_hdl));
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vTaskDelay(5);
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}
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xSemaphoreGive(test_done_semphr);
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vTaskDelete(NULL);
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}
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#endif
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// This case is now tested only manually
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TEST_CASE("GPIO output internal clock", "[gpio_output_clock][ignore]")
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{
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test_done_semphr = xSemaphoreCreateCounting(3, 0);
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xTaskCreate(&output_clock_1, "output_clock_1", 4096, NULL, 4, NULL);
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xTaskCreate(&output_clock_2, "output_clock_2", 4096, NULL, 4, NULL);
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#if SOC_GPIO_CLOCKOUT_CHANNEL_NUM >= 3
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xTaskCreate(&output_clock_3, "output_clock_3", 4096, NULL, 4, NULL);
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#endif
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int cnt = 0;
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while (cnt < SOC_GPIO_CLOCKOUT_CHANNEL_NUM) {
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if (xSemaphoreTake(test_done_semphr, portMAX_DELAY) == pdTRUE) {
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cnt++;
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}
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}
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vTaskDelay(1);
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vSemaphoreDelete(test_done_semphr);
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#if CONFIG_IDF_TARGET_ESP32
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/* ESP32 clock out channel pin reuses UART TX/RX pin, restore its default
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configuration at the end of the test */
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gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD);
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gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_U0TXD);
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#endif
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}
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#if SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
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TEST_CASE("GPIO output internal clock one-to-many", "[gpio_output_clock][ignore]")
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{
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// Test NULL handle assertion
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TEST_ESP_ERR(esp_clock_output_start(test_clk_out_sig[0], test_clk_out_io[0], NULL), ESP_ERR_INVALID_ARG);
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// Test first mapping
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esp_clock_output_mapping_handle_t clkout_mapping_hdl_0;
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TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[0], test_clk_out_io[0], &clkout_mapping_hdl_0)); // [0]:0(1) [1]:x [2]:x
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// Test the same mapping allocate the same handle
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esp_clock_output_mapping_handle_t clkout_mapping_hdl_1;
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TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[0], test_clk_out_io[0], &clkout_mapping_hdl_1)); // [0]:0(2) [1]:x [2]:x
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TEST_ASSERT(clkout_mapping_hdl_0 == clkout_mapping_hdl_1);
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// Test map multi signal to one IO assertion
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esp_clock_output_mapping_handle_t clkout_mapping_hdl_2;
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TEST_ESP_ERR(esp_clock_output_start(test_clk_out_sig[1], test_clk_out_io[0], &clkout_mapping_hdl_2), ESP_ERR_INVALID_ARG);
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// Test the same signal mapping to multi GPIO
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TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[0], test_clk_out_io[1], &clkout_mapping_hdl_2)); // [0]:0(2) 1 [1]:x [2]:x
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esp_clock_output_mapping_handle_t clkout_mapping_hdl_3;
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TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[0], test_clk_out_io[2], &clkout_mapping_hdl_3)); // [0]:0(2) 1 2 [1]:x [2]:x
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// Test the clkout mapping ref_cnt validity
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esp_clock_output_stop(clkout_mapping_hdl_0); // [0]:0(1) 1 2 [1]:x [2]:x
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esp_clock_output_mapping_handle_t clkout_mapping_hdl_4;
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TEST_ESP_ERR(esp_clock_output_start(test_clk_out_sig[1], test_clk_out_io[0], &clkout_mapping_hdl_4), ESP_ERR_INVALID_ARG);
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esp_clock_output_stop(clkout_mapping_hdl_1); // [0]:1 2 [1]:x [2]:x
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TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[1], test_clk_out_io[0], &clkout_mapping_hdl_4)); // [0]:1 2 [1]:0 [2]:x
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#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3
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test_clk_out_sig[3] = CLKOUT_SIG_PLL_F80M;
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#else
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test_clk_out_sig[3] = CLKOUT_SIG_RC_32K;
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#endif
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// Test the excess clock channel request assertion
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esp_clock_output_stop(clkout_mapping_hdl_3); // [0]:1 [1]:0 [2]:x
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esp_clock_output_mapping_handle_t clkout_mapping_hdl_5;
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TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[2], test_clk_out_io[2], &clkout_mapping_hdl_5)); // [0]:1 [1]:0 [2]:2
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esp_clock_output_mapping_handle_t clkout_mapping_hdl_6;
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TEST_ASSERT(ESP_FAIL == esp_clock_output_start(test_clk_out_sig[3], test_clk_out_io[3], &clkout_mapping_hdl_6));
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// Test the clock out channel recycle
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esp_clock_output_stop(clkout_mapping_hdl_4); // [0]:1 [1]:x [2]:2
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esp_clock_output_mapping_handle_t clkout_mapping_hdl_7;
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TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[3], test_clk_out_io[0], &clkout_mapping_hdl_7)); // [0]:1 [1]:0 [2]:2
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// Stop all
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esp_clock_output_stop(clkout_mapping_hdl_2);
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esp_clock_output_stop(clkout_mapping_hdl_5);
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esp_clock_output_stop(clkout_mapping_hdl_6);
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esp_clock_output_stop(clkout_mapping_hdl_7);
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}
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#endif
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