kopia lustrzana https://github.com/espressif/esp-idf
79 wiersze
2.0 KiB
C
79 wiersze
2.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "bootloader_random.h"
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#include "esp_cpu.h"
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#include "soc/wdev_reg.h"
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#ifndef BOOTLOADER_BUILD
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#include "esp_random.h"
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#include "esp_private/periph_ctrl.h"
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__attribute__((weak)) void bootloader_fill_random(void *buffer, size_t length)
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{
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return esp_fill_random(buffer, length);
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}
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#else
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#if !defined CONFIG_IDF_TARGET_ESP32S3
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#define RNG_CPU_WAIT_CYCLE_NUM (80 * 32 * 2) /* extra factor of 2 is precautionary */
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#else
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#define RNG_CPU_WAIT_CYCLE_NUM (80 * 23) /* 45 KHz reading frequency is the maximum we have tested so far on S3 */
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#endif
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__attribute__((weak)) void bootloader_fill_random(void *buffer, size_t length)
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{
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uint8_t *buffer_bytes = (uint8_t *)buffer;
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uint32_t random;
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uint32_t start, now;
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assert(buffer != NULL);
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for (size_t i = 0; i < length; i++) {
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if (i == 0 || i % 4 == 0) { /* redundant check is for a compiler warning */
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/* in bootloader with ADC feeding HWRNG, we accumulate 1
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bit of entropy per 40 APB cycles (==80 CPU cycles.)
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To avoid reading the entire RNG hardware state out
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as-is, we repeatedly read the RNG register and XOR all
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values.
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*/
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random = REG_READ(WDEV_RND_REG);
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start = esp_cpu_get_cycle_count();
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do {
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random ^= REG_READ(WDEV_RND_REG);
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now = esp_cpu_get_cycle_count();
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} while (now - start < RNG_CPU_WAIT_CYCLE_NUM);
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}
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buffer_bytes[i] = random >> ((i % 4) * 8);
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}
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}
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#ifndef CONFIG_IDF_ENV_FPGA
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#else // CONFIG_IDF_ENV_FPGA
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#include "esp_log.h"
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static void s_non_functional(const char *func)
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{
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ESP_EARLY_LOGW("rand", "%s non-functional for FPGA builds", func);
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}
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void bootloader_random_enable()
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{
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s_non_functional(__func__);
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}
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void bootloader_random_disable()
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{
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s_non_functional(__func__);
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}
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#endif // CONFIG_IDF_ENV_FPGA
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#endif // BOOTLOADER_BUILD
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