kopia lustrzana https://github.com/espressif/esp-idf
55 wiersze
3.2 KiB
C
55 wiersze
3.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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//+-----------------------------------------------Terminology---------------------------------------------+
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//| |
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//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
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//| |
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//| Core Reset: Reset the whole digital system except RTC sub-system |
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//| |
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//| System Reset: Reset the whole digital system, including RTC sub-system |
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//| |
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//| Chip Reset: Reset the whole chip, including the analog part |
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//| |
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//+-------------------------------------------------------------------------------------------------------+
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
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* @note refer to TRM: <Reset and Clock> chapter
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*/
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typedef enum {
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RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
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RESET_REASON_CORE_SW = 0x03, // Software resets the digital core
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RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core, check when doing sleep bringup
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RESET_REASON_CORE_PMU_PWR_DOWN = 0x05, // PMU HP power down core reset
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RESET_REASON_CORE_MWDT = 0x07, // MWDT core reset
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RESET_REASON_CORE_RWDT = 0x09, // RWDT core reset
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RESET_REASON_CPU_MWDT = 0x0B, // MWDT HP CPU 0/1 reset
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RESET_REASON_CPU_SW = 0x0C, // Software resets HP CPU 0/1
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RESET_REASON_CPU0_SW = 0x0C, // Software resets HP CPU 0, kept to be compatible with older chips
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RESET_REASON_CPU_RWDT = 0x0D, // RWDT resets digital core
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RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
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RESET_REASON_SYS_RWDT = 0x10, // RWDT system reset
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RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
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RESET_REASON_CORE_PWR_GLITCH = 0x13, // Glitch on power resets the digital core and rtc module
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RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
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RESET_REASON_CORE_USB_JTAG = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core
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RESET_REASON_CORE_USB_UART = 0x17, // USB Serial/JTAG controller's UART resets the digital core
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RESET_REASON_CPU_JTAG = 0x18, // Triggered when a reset command from JTAG is received
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RESET_REASON_CPU_LOCKUP = 0x1A, // Triggered when the CPU enters lockup (exception inside the execption handler would cause this)
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} soc_reset_reason_t;
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#ifdef __cplusplus
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}
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#endif
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