kopia lustrzana https://github.com/espressif/esp-idf
131 wiersze
5.4 KiB
C
131 wiersze
5.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <stdlib.h>
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#include "esp32c61/rom/ets_sys.h"
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#include "esp32c61/rom/rtc.h"
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#include "esp32c61/rom/uart.h"
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#include "soc/rtc.h"
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#include "esp_cpu.h"
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#include "regi2c_ctrl.h"
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#include "soc/lp_clkrst_reg.h"
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#include "soc/regi2c_dig_reg.h"
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#include "esp_hw_log.h"
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#include "sdkconfig.h"
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#include "esp_rom_uart.h"
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#include "esp_private/esp_pmu.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/pmu_ll.h"
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#if SOC_MODEM_CLOCK_SUPPORTED //TODO: [ESP32C61] IDF-9513
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#include "hal/modem_syscon_ll.h"
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#include "hal/modem_lpcon_ll.h"
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#endif
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#include "soc/pmu_reg.h"
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#include "pmu_param.h"
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static const char *TAG = "rtc_clk_init";
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/**
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* Initialize the ICG map of some modem clock domains in the PMU_ACTIVE state
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*
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* A pre-initialization interface is used to initialize the ICG map of the
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* MODEM_APB, I2C_MST and LP_APB clock domains in the PMU_ACTIVE state, and
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* disable the clock gating of these clock domains in the PMU_ACTIVE state,
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* because the system clock source (PLL) in the system boot up process needs
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* to use the i2c master peripheral.
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*
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* ICG map of all modem clock domains under different power states (PMU_ACTIVE,
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* PMU_MODEM and PMU_SLEEP) will be initialized in esp_perip_clk_init().
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*/
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static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void)
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{
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/* Configure modem ICG code in PMU_ACTIVE state */
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pmu_ll_hp_set_icg_modem(&PMU, PMU_MODE_HP_ACTIVE, PMU_HP_ICG_MODEM_CODE_ACTIVE);
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// TODO: [ESP32C61] IDF-9513, modem support
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#if SOC_MODEM_CLOCK_SUPPORTED
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/* Disable clock gating for MODEM_APB, I2C_MST and LP_APB clock domains in PMU_ACTIVE state */
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modem_syscon_ll_set_modem_apb_icg_bitmap(&MODEM_SYSCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
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modem_lpcon_ll_set_i2c_master_icg_bitmap(&MODEM_LPCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
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modem_lpcon_ll_set_lp_apb_icg_bitmap(&MODEM_LPCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
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#endif
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/* Software trigger force update modem ICG code and ICG switch */
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pmu_ll_imm_update_dig_icg_modem_code(&PMU, true);
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pmu_ll_imm_update_dig_icg_switch(&PMU, true);
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}
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void rtc_clk_init(rtc_clk_config_t cfg)
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{
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rtc_cpu_freq_config_t old_config, new_config;
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rtc_clk_modem_clock_domain_active_state_icg_map_preinit();
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/* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks.
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* Note: this doesn't attempt to set the clocks to precise frequencies.
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* Instead, we calibrate these clocks against XTAL frequency later, when necessary.
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* - SCK_DCAP value controls tuning of RC_SLOW clock.
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* The higher the value of DCAP is, the lower is the frequency.
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* - CK8M_DFREQ value controls tuning of RC_FAST clock.
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* CLK_8M_DFREQ constant gives the best temperature characteristics.
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* - RC32K_DFREQ value controls tuning of RC32K clock.
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*/
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REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap);
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REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
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uint32_t hp_cali_dbias = get_act_hp_dbias();
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uint32_t lp_cali_dbias = get_act_lp_dbias();
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SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
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SET_PERI_REG_BITS(PMU_HP_MODEM_HP_REGULATOR0_REG, PMU_HP_MODEM_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S);
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SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
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clk_ll_rc_fast_tick_conf();
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soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
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esp_rom_output_tx_wait_idle(0);
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rtc_clk_xtal_freq_update(xtal_freq);
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// On ESP32C61, MSPI source clock's default HS divider leads to 120MHz, which is unusable before calibration
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// Therefore, before switching SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider to make it run at
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// 80MHz after the switch. PLL = 480MHz, so divider is 6.
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clk_ll_mspi_fast_set_hs_divider(6);
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/* Set CPU frequency */
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rtc_clk_cpu_freq_get_config(&old_config);
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uint32_t freq_before = old_config.freq_mhz;
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bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
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if (!res) {
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ESP_HW_LOGE(TAG, "invalid CPU frequency value");
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abort();
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}
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rtc_clk_cpu_freq_set_config(&new_config);
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/* Re-calculate the ccount to make time calculation correct. */
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esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
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/* Slow & fast clocks setup */
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// We will not power off RC_FAST in bootloader stage even if it is not being used as any
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// cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
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bool need_rc_fast_en = true;
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if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
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rtc_clk_32k_enable(true);
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} else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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rtc_clk_32k_enable_external();
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} else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
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rtc_clk_rc32k_enable(true);
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}
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rtc_clk_8m_enable(need_rc_fast_en);
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rtc_clk_fast_src_set(cfg.fast_clk_src);
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rtc_clk_slow_src_set(cfg.slow_clk_src);
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}
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