kopia lustrzana https://github.com/espressif/esp-idf
75 wiersze
2.1 KiB
C
75 wiersze
2.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "ulp_riscv_utils.h"
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#include "ulp_riscv_register_ops.h"
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#include "soc/soc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/soc_ulp.h"
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#include "soc/sens_reg.h"
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void ulp_riscv_rescue_from_monitor(void)
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{
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/* Rescue RISCV from monitor state. */
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN);
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}
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void ulp_riscv_wakeup_main_processor(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SW_CPU_INT);
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}
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void ulp_riscv_halt(void)
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{
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/* Setting the delay time after RISCV recv `DONE` signal, Ensure that action `RESET` can be executed in time. */
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REG_SET_FIELD(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_2_CLK_DIS, 0x3F);
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/* Suspends the ulp operation and reset the ULP core. Must be the final operation before going to halt. */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN);
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while (1);
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}
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void ulp_riscv_timer_stop(void)
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{
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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}
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void ulp_riscv_timer_resume(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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}
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void ulp_riscv_gpio_wakeup_clear(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR);
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}
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void ulp_riscv_enable_sw_intr(intr_handler_t handler, void *arg)
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{
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/* Enable ULP RISC-V SW interrupt */
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SET_PERI_REG_MASK(SENS_SAR_COCPU_INT_ENA_REG, SENS_COCPU_SW_INT_ENA);
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/* Register interrupt handler */
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if (handler) {
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ulp_riscv_intr_alloc(ULP_RISCV_SW_INTR_SOURCE, handler, arg);
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}
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}
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void ulp_riscv_disable_sw_intr(void)
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{
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/* Disable ULP RISC-V SW interrupt */
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CLEAR_PERI_REG_MASK(SENS_SAR_COCPU_INT_ENA_REG, SENS_COCPU_SW_INT_ENA);
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/* De-register interrupt handler */
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ulp_riscv_intr_free(ULP_RISCV_SW_INTR_SOURCE);
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}
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void ulp_riscv_trigger_sw_intr(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SW_INT_TRIGGER);
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}
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