kopia lustrzana https://github.com/espressif/esp-idf
123 wiersze
5.7 KiB
C
123 wiersze
5.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <inttypes.h>
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#include "esp_assert.h"
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// TODO: IDF-9197
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#include "sdkconfig.h"
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/**
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* @brief ESP chip ID
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*
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*/
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typedef enum {
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ESP_CHIP_ID_ESP32 = 0x0000, /*!< chip ID: ESP32 */
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ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */
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ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
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ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */
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ESP_CHIP_ID_ESP32C2 = 0x000C, /*!< chip ID: ESP32-C2 */
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ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
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ESP_CHIP_ID_ESP32H2 = 0x0010, /*!< chip ID: ESP32-H2 */
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ESP_CHIP_ID_ESP32P4 = 0x0012, /*!< chip ID: ESP32-P4 */
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#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-9197
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ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 beta3 (MPW)*/
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#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
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ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 MP */
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#endif
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ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
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} __attribute__((packed)) esp_chip_id_t;
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/** @cond */
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ESP_STATIC_ASSERT(sizeof(esp_chip_id_t) == 2, "esp_chip_id_t should be 16 bit");
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/** @endcond */
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/**
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* @brief SPI flash mode, used in esp_image_header_t
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*/
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typedef enum {
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ESP_IMAGE_SPI_MODE_QIO, /*!< SPI mode QIO */
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ESP_IMAGE_SPI_MODE_QOUT, /*!< SPI mode QOUT */
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ESP_IMAGE_SPI_MODE_DIO, /*!< SPI mode DIO */
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ESP_IMAGE_SPI_MODE_DOUT, /*!< SPI mode DOUT */
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ESP_IMAGE_SPI_MODE_FAST_READ, /*!< SPI mode FAST_READ */
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ESP_IMAGE_SPI_MODE_SLOW_READ /*!< SPI mode SLOW_READ */
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} esp_image_spi_mode_t;
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/**
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* @brief SPI flash clock division factor.
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*/
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typedef enum {
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ESP_IMAGE_SPI_SPEED_DIV_2, /*!< The SPI flash clock frequency is divided by 2 of the clock source */
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ESP_IMAGE_SPI_SPEED_DIV_3, /*!< The SPI flash clock frequency is divided by 3 of the clock source */
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ESP_IMAGE_SPI_SPEED_DIV_4, /*!< The SPI flash clock frequency is divided by 4 of the clock source */
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ESP_IMAGE_SPI_SPEED_DIV_1 = 0xF /*!< The SPI flash clock frequency equals to the clock source */
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} esp_image_spi_freq_t;
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/**
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* @brief Supported SPI flash sizes
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*/
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typedef enum {
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ESP_IMAGE_FLASH_SIZE_1MB = 0, /*!< SPI flash size 1 MB */
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ESP_IMAGE_FLASH_SIZE_2MB, /*!< SPI flash size 2 MB */
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ESP_IMAGE_FLASH_SIZE_4MB, /*!< SPI flash size 4 MB */
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ESP_IMAGE_FLASH_SIZE_8MB, /*!< SPI flash size 8 MB */
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ESP_IMAGE_FLASH_SIZE_16MB, /*!< SPI flash size 16 MB */
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ESP_IMAGE_FLASH_SIZE_32MB, /*!< SPI flash size 32 MB */
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ESP_IMAGE_FLASH_SIZE_64MB, /*!< SPI flash size 64 MB */
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ESP_IMAGE_FLASH_SIZE_128MB, /*!< SPI flash size 128 MB */
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ESP_IMAGE_FLASH_SIZE_MAX /*!< SPI flash size MAX */
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} esp_image_flash_size_t;
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#define ESP_IMAGE_HEADER_MAGIC 0xE9 /*!< The magic word for the esp_image_header_t structure. */
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/**
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* @brief Main header of binary image
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*/
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typedef struct {
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uint8_t magic; /*!< Magic word ESP_IMAGE_HEADER_MAGIC */
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uint8_t segment_count; /*!< Count of memory segments */
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uint8_t spi_mode; /*!< flash read mode (esp_image_spi_mode_t as uint8_t) */
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uint8_t spi_speed: 4; /*!< flash frequency (esp_image_spi_freq_t as uint8_t) */
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uint8_t spi_size: 4; /*!< flash chip size (esp_image_flash_size_t as uint8_t) */
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uint32_t entry_addr; /*!< Entry address */
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uint8_t wp_pin; /*!< WP pin when SPI pins set via efuse (read by ROM bootloader,
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* the IDF bootloader uses software to configure the WP
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* pin and sets this field to 0xEE=disabled) */
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uint8_t spi_pin_drv[3]; /*!< Drive settings for the SPI flash pins (read by ROM bootloader) */
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esp_chip_id_t chip_id; /*!< Chip identification number */
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uint8_t min_chip_rev; /*!< Minimal chip revision supported by image
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* After the Major and Minor revision eFuses were introduced into the chips, this field is no longer used.
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* But for compatibility reasons, we keep this field and the data in it.
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* Use min_chip_rev_full instead.
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* The software interprets this as a Major version for most of the chips and as a Minor version for the ESP32-C3.
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*/
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uint16_t min_chip_rev_full; /*!< Minimal chip revision supported by image, in format: major * 100 + minor */
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uint16_t max_chip_rev_full; /*!< Maximal chip revision supported by image, in format: major * 100 + minor */
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uint8_t reserved[4]; /*!< Reserved bytes in additional header space, currently unused */
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uint8_t hash_appended; /*!< If 1, a SHA256 digest "simple hash" (of the entire image) is appended after the checksum.
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* Included in image length. This digest
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* is separate to secure boot and only used for detecting corruption.
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* For secure boot signed images, the signature
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* is appended after this (and the simple hash is included in the signed data). */
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} __attribute__((packed)) esp_image_header_t;
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/** @cond */
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ESP_STATIC_ASSERT(sizeof(esp_image_header_t) == 24, "binary image header should be 24 bytes");
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/** @endcond */
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/**
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* @brief Header of binary image segment
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*/
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typedef struct {
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uint32_t load_addr; /*!< Address of segment */
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uint32_t data_len; /*!< Length of data */
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} esp_image_segment_header_t;
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#define ESP_IMAGE_MAX_SEGMENTS 16 /*!< Max count of segments in the image. */
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