kopia lustrzana https://github.com/espressif/esp-idf
504 wiersze
16 KiB
C
504 wiersze
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <assert.h>
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#include <stdlib.h>
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#include "sdkconfig.h"
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#include "esp32p4/rom/rtc.h"
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#include "soc/rtc.h"
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#include "esp_private/rtc_clk.h"
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#include "esp_hw_log.h"
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#include "esp_rom_sys.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/regi2c_ctrl_ll.h"
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#include "hal/gpio_ll.h"
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#include "soc/io_mux_reg.h"
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#include "esp_private/sleep_event.h"
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static const char *TAG = "rtc_clk";
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// CPLL frequency option, in 360/400MHz. Zero if CPLL is not enabled.
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static int s_cur_cpll_freq = 0;
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void rtc_clk_32k_enable(bool enable)
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{
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if (enable) {
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clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL);
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} else {
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clk_ll_xtal32k_disable();
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}
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}
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void rtc_clk_32k_bootstrap(uint32_t cycle)
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{
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/* No special bootstrapping needed for ESP32-P4, 'cycle' argument is to keep the signature
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* same as for the ESP32. Just enable the XTAL here.
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*/
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(void)cycle;
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rtc_clk_32k_enable(true);
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}
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bool rtc_clk_32k_enabled(void)
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{
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return clk_ll_xtal32k_is_enabled();
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}
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void rtc_clk_rc32k_enable(bool enable)
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{
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if (enable) {
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clk_ll_rc32k_enable();
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esp_rom_delay_us(SOC_DELAY_RC32K_ENABLE);
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} else {
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clk_ll_rc32k_disable();
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}
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}
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void rtc_clk_8m_enable(bool clk_8m_en)
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{
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if (clk_8m_en) {
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clk_ll_rc_fast_enable();
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esp_rom_delay_us(SOC_DELAY_RC_FAST_ENABLE);
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} else {
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clk_ll_rc_fast_disable();
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}
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}
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bool rtc_clk_8m_enabled(void)
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{
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return clk_ll_rc_fast_is_enabled();
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}
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void rtc_clk_lp_pll_enable(bool enable)
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{
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if (enable) {
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clk_ll_lp_pll_enable();
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esp_rom_delay_us(SOC_DELAY_LP_PLL_ENABLE);
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} else {
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clk_ll_lp_pll_disable();
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}
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}
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void rtc_clk_lp_pll_src_set(soc_lp_pll_clk_src_t clk_src)
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{
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clk_ll_lp_pll_set_src(clk_src);
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esp_rom_delay_us(SOC_DELAY_LP_PLL_SWITCH);
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}
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void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
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{
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clk_ll_rtc_slow_set_src(clk_src);
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esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH);
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}
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soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
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{
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return clk_ll_rtc_slow_get_src();
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}
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uint32_t rtc_clk_slow_freq_get_hz(void)
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{
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switch (rtc_clk_slow_src_get()) {
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case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX;
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default: return 0;
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}
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}
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void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src)
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{
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clk_ll_rtc_fast_set_src(clk_src);
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esp_rom_delay_us(SOC_DELAY_RTC_FAST_CLK_SWITCH);
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}
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soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)
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{
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return clk_ll_rtc_fast_get_src();
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}
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static void rtc_clk_cpll_disable(void)
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{
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clk_ll_cpll_disable();
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s_cur_cpll_freq = 0;
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}
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static void rtc_clk_cpll_enable(void)
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{
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clk_ll_cpll_enable();
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}
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static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq)
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{
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/* Digital part */
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clk_ll_cpll_set_freq_mhz(cpll_freq);
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/* Analog part */
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/* CPLL CALIBRATION START */
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regi2c_ctrl_ll_cpll_calibration_start();
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clk_ll_cpll_set_config(cpll_freq, xtal_freq);
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/* WAIT CALIBRATION DONE */
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while(!regi2c_ctrl_ll_cpll_calibration_is_done());
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esp_rom_delay_us(10); // wait for true stop
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/* CPLL CALIBRATION STOP */
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regi2c_ctrl_ll_cpll_calibration_stop();
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s_cur_cpll_freq = cpll_freq;
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}
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/**
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* Switch to use XTAL as the CPU clock source.
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* Must satisfy: cpu_freq = XTAL_FREQ / div.
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* Does not disable the PLL.
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*
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* If to_default is set, then will configure CPU - MEM - SYS - APB frequencies back to power-on reset configuration (40 - 20 - 20 - 10)
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* If to_default is not set, then will configure to 40 - 40 - 40 - 40
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*/
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static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div, bool to_default)
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{
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// let f_cpu = f_mem = f_sys = f_apb
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uint32_t mem_divider = 1;
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uint32_t sys_divider = 1;
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uint32_t apb_divider = 1;
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if (to_default) {
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// f_cpu = 2 * f_mem = 2 * f_sys = 4 * f_apb
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mem_divider = 2;
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apb_divider = 2;
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}
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// Update bit does not control CPU clock sel mux. Therefore, there will be a middle state during the switch (CPU falls)
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// Since before the switch, the clock source is CPLL, there is divider value constraints.
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// Setting the new dividers first is unguaranteed (hardware could automatically modify the real dividers)
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// Therefore, we will switch cpu clock source first, and then set the desired dividers.
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
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clk_ll_cpu_set_divider(div, 0, 0);
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clk_ll_mem_set_divider(mem_divider);
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clk_ll_sys_set_divider(sys_divider);
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clk_ll_apb_set_divider(apb_divider);
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clk_ll_bus_update();
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esp_rom_set_cpu_ticks_per_us(cpu_freq);
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}
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static void rtc_clk_cpu_freq_to_8m(void)
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{
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// let f_cpu = f_mem = f_sys = f_apb
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clk_ll_cpu_set_divider(1, 0, 0);
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clk_ll_mem_set_divider(1);
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clk_ll_sys_set_divider(1);
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clk_ll_apb_set_divider(1);
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
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clk_ll_bus_update();
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esp_rom_set_cpu_ticks_per_us(20);
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}
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/**
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* Switch to one of CPLL-based frequencies. Current frequency can be XTAL or CPLL.
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* CPLL must already be enabled.
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* @param cpu_freq new CPU frequency
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*/
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static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *div)
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{
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// CPLL -> CPU_CLK -> MEM_CLK -> SYS_CLK -> APB_CLK
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// Constraint: MEM_CLK <= 200MHz, APB_CLK <= 100MHz
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// This implies that when clock source is CPLL,
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// If cpu_divider < 2, mem_divider must be larger or equal to 2
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// If cpu_divider < 2, mem_divider = 2, sys_divider < 2, apb_divider must be larger or equal to 2
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// Current available configurations:
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// 360 - 360 - 180 - 180 - 90
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// 360 - 180 - 180 - 180 - 90
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// 360 - 90 - 90 - 90 - 90
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uint32_t mem_divider = 1;
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uint32_t sys_divider = 1; // We are not going to change this
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uint32_t apb_divider = 1;
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switch (cpu_freq_mhz) {
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case 360:
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mem_divider = 2;
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apb_divider = 2;
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break;
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case 180:
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mem_divider = 1;
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apb_divider = 2;
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break;
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case 90:
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mem_divider = 1;
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apb_divider = 1;
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break;
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default:
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// Unsupported configuration
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// This is dangerous to modify dividers. Hardware could automatically correct the divider, and it won't be
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// reflected to the registers. Therefore, you won't even be able to calculate out the real mem_clk, apb_clk freq.
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// To avoid such case, we will strictly do abort here.
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abort();
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}
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// Update bit does not control CPU clock sel mux. Therefore, there may be a middle state during the switch (CPU rises)
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// Since this is upscaling, we need to configure the frequency division coefficient before switching the clock source.
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// Otherwise, an intermediate state will occur, in the intermediate state, the frequency of APB/MEM does not meet the
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// timing requirements. If there are periperals/CPU access that depend on these two clocks at this moment, some exception
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// might occur.
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clk_ll_cpu_set_divider(div->integer, div->numerator, div->denominator);
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clk_ll_mem_set_divider(mem_divider);
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clk_ll_sys_set_divider(sys_divider);
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clk_ll_apb_set_divider(apb_divider);
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clk_ll_bus_update();
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
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esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
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}
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bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
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{
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uint32_t source_freq_mhz;
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soc_cpu_clk_src_t source;
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hal_utils_clk_div_t divider = {0}; // divider = freq of HP_ROOT_CLK / freq of CPU_CLK
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uint32_t real_freq_mhz;
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// Keep default CPLL at 360MHz
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uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
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if (freq_mhz <= xtal_freq && freq_mhz != 0) {
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divider.integer = xtal_freq / freq_mhz;
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real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */
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if (real_freq_mhz != freq_mhz) {
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// no suitable divider
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return false;
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}
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source_freq_mhz = xtal_freq;
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source = SOC_CPU_CLK_SRC_XTAL;
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} else if (freq_mhz == 90) {
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real_freq_mhz = freq_mhz;
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source = SOC_CPU_CLK_SRC_CPLL;
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source_freq_mhz = CLK_LL_PLL_360M_FREQ_MHZ;
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divider.integer = 4;
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} else if (freq_mhz == 180) {
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real_freq_mhz = freq_mhz;
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source = SOC_CPU_CLK_SRC_CPLL;
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source_freq_mhz = CLK_LL_PLL_360M_FREQ_MHZ;
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divider.integer = 2;
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} else if (freq_mhz == 360) {
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real_freq_mhz = freq_mhz;
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source = SOC_CPU_CLK_SRC_CPLL;
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source_freq_mhz = CLK_LL_PLL_360M_FREQ_MHZ;
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divider.integer = 1;
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} else if (freq_mhz == 400) {
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// If CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ selects 400MHz, then at app startup stage will need a CPLL calibration to raise its freq from 360MHz to 400MHz
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real_freq_mhz = freq_mhz;
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source = SOC_CPU_CLK_SRC_CPLL;
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source_freq_mhz = CLK_LL_PLL_400M_FREQ_MHZ;
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divider.integer = 1;
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} else {
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// unsupported frequency
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return false;
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}
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*out_config = (rtc_cpu_freq_config_t) {
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.source = source,
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.div = divider,
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.source_freq_mhz = source_freq_mhz,
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.freq_mhz = real_freq_mhz
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};
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return true;
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}
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__attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
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{
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}
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void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
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{
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soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
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if (config->source == SOC_CPU_CLK_SRC_XTAL) {
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rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div.integer, false);
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if (old_cpu_clk_src == SOC_CPU_CLK_SRC_CPLL) {
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rtc_clk_cpll_disable();
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}
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} else if (config->source == SOC_CPU_CLK_SRC_CPLL) {
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if (old_cpu_clk_src != SOC_CPU_CLK_SRC_CPLL) {
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
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rtc_clk_cpll_enable();
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}
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if (config->source_freq_mhz != s_cur_cpll_freq) {
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soc_xtal_freq_t xtal_freq_mhz = rtc_clk_xtal_freq_get();
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// Calibrate CPLL freq to a new value requires to switch CPU clock source to XTAL first
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rtc_clk_cpu_freq_to_xtal((uint32_t)xtal_freq_mhz, 1, false);
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rtc_clk_cpll_configure(xtal_freq_mhz, config->source_freq_mhz);
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}
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rtc_clk_cpu_freq_to_cpll_mhz(config->freq_mhz, (hal_utils_clk_div_t *)&config->div);
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
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} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
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rtc_clk_cpu_freq_to_8m();
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if (old_cpu_clk_src == SOC_CPU_CLK_SRC_CPLL) {
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rtc_clk_cpll_disable();
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}
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}
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}
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void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t source_freq_mhz;
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hal_utils_clk_div_t div = {0}; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
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uint32_t freq_mhz;
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clk_ll_cpu_get_divider(&div.integer, &div.numerator, &div.denominator);
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if (div.denominator == 0) {
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div.denominator = 1;
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div.numerator = 0;
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}
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switch (source) {
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case SOC_CPU_CLK_SRC_XTAL: {
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source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
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break;
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}
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case SOC_CPU_CLK_SRC_CPLL: {
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source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get());
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break;
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}
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case SOC_CPU_CLK_SRC_RC_FAST:
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source_freq_mhz = 20;
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break;
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default:
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ESP_HW_LOGE(TAG, "unsupported frequency configuration");
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abort();
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}
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freq_mhz = source_freq_mhz * div.denominator / (div.integer * div.denominator + div.numerator);
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*out_config = (rtc_cpu_freq_config_t) {
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.source = source,
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.source_freq_mhz = source_freq_mhz,
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.div = div,
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.freq_mhz = freq_mhz
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};
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}
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void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
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{
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if (config->source == SOC_CPU_CLK_SRC_XTAL) {
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rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div.integer, false);
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} else if (config->source == SOC_CPU_CLK_SRC_CPLL &&
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s_cur_cpll_freq == config->source_freq_mhz) {
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rtc_clk_cpu_freq_to_cpll_mhz(config->freq_mhz, (hal_utils_clk_div_t *)&config->div);
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} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
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rtc_clk_cpu_freq_to_8m();
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} else {
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/* fallback */
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rtc_clk_cpu_freq_set_config(config);
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}
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}
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void rtc_clk_cpu_freq_set_xtal(void)
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{
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int freq_mhz = (int)rtc_clk_xtal_freq_get();
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rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, false);
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rtc_clk_cpll_disable();
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}
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void rtc_clk_cpu_set_to_default_config(void)
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{
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int freq_mhz = (int)rtc_clk_xtal_freq_get();
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rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, true);
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}
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soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
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{
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uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
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if (xtal_freq_mhz == 0) {
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ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
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return SOC_XTAL_FREQ_40M;
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}
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return (soc_xtal_freq_t)xtal_freq_mhz;
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}
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void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
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{
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clk_ll_xtal_store_freq_mhz(xtal_freq);
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}
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uint32_t rtc_clk_apb_freq_get(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t source_freq_mhz;
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switch (source) {
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case SOC_CPU_CLK_SRC_XTAL:
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source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
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break;
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case SOC_CPU_CLK_SRC_CPLL:
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source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get());
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break;
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case SOC_CPU_CLK_SRC_RC_FAST:
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source_freq_mhz = 20;
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break;
|
|
default:
|
|
// Unknown HP_ROOT clock source
|
|
source_freq_mhz = 0;
|
|
ESP_HW_LOGE(TAG, "Invalid HP_ROOT_CLK");
|
|
break;
|
|
}
|
|
uint32_t integer, numerator, denominator;
|
|
clk_ll_cpu_get_divider(&integer, &numerator, &denominator);
|
|
if (denominator == 0) {
|
|
denominator = 1;
|
|
numerator = 0;
|
|
}
|
|
uint32_t cpu_freq_hz = source_freq_mhz * MHZ * denominator / (integer * denominator + numerator);
|
|
uint32_t mem_freq_hz = cpu_freq_hz / clk_ll_mem_get_divider();
|
|
uint32_t sys_freq_hz = mem_freq_hz / clk_ll_sys_get_divider();
|
|
return sys_freq_hz / clk_ll_apb_get_divider();
|
|
}
|
|
|
|
void rtc_clk_apll_enable(bool enable)
|
|
{
|
|
// TODO: IDF-8884
|
|
}
|
|
|
|
uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2)
|
|
{
|
|
// TODO: IDF-8884
|
|
return 0;
|
|
}
|
|
|
|
void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
|
|
{
|
|
// TODO: IDF-8884
|
|
}
|
|
|
|
void rtc_dig_clk8m_enable(void)
|
|
{
|
|
clk_ll_rc_fast_digi_enable();
|
|
esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
|
|
}
|
|
|
|
void rtc_dig_clk8m_disable(void)
|
|
{
|
|
clk_ll_rc_fast_digi_disable();
|
|
esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
|
|
}
|
|
|
|
bool rtc_dig_8m_enabled(void)
|
|
{
|
|
return clk_ll_rc_fast_digi_is_enabled();
|
|
}
|
|
|
|
//------------------------------------MPLL-------------------------------------//
|
|
void rtc_clk_mpll_disable(void)
|
|
{
|
|
clk_ll_mpll_disable();
|
|
}
|
|
|
|
void rtc_clk_mpll_enable(void)
|
|
{
|
|
clk_ll_mpll_enable();
|
|
}
|
|
|
|
void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
|
|
{
|
|
/* Analog part */
|
|
/* MPLL calibration start */
|
|
regi2c_ctrl_ll_mpll_calibration_start();
|
|
clk_ll_mpll_set_config(mpll_freq, xtal_freq);
|
|
/* wait calibration done */
|
|
while(!regi2c_ctrl_ll_mpll_calibration_is_done());
|
|
/* MPLL calibration stop */
|
|
regi2c_ctrl_ll_mpll_calibration_stop();
|
|
}
|