kopia lustrzana https://github.com/espressif/esp-idf
133 wiersze
3.7 KiB
C
133 wiersze
3.7 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "soc/soc.h"
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#include "soc/interrupt_core0_reg.h"
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#include "riscv/interrupt.h"
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#include "riscv/csr.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief enable interrupts specified by the mask
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*
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* @param mask bitmask of interrupts that needs to be enabled
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*/
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static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask)
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{
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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esprv_intc_int_enable(mask);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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}
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/**
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* @brief disable interrupts specified by the mask
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*
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* @param mask bitmask of interrupts that needs to be disabled
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*/
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static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask)
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{
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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esprv_intc_int_disable(mask);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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}
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/**
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* @brief Read the current interrupt mask of the CPU running this code.
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*
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* @return The current interrupt bitmask.
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*/
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static inline uint32_t intr_cntrl_ll_read_interrupt_mask(void)
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{
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return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
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}
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/**
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* @brief checks if given interrupt number has a valid handler
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*
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* @param intr interrupt number ranged from 0 to 31
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* @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1
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* @return true for valid handler, false otherwise
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*/
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static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
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{
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return intr_handler_get(intr);
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}
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/**
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* @brief sets interrupt handler and optional argument of a given interrupt number
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*
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* @param intr interrupt number ranged from 0 to 31
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* @param handler handler invoked when an interrupt occurs
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* @param arg optional argument to pass to the handler
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*/
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static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
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{
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intr_handler_set(intr, (void *)handler, arg);
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}
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/**
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* @brief Gets argument passed to handler of a given interrupt number
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*
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* @param intr interrupt number ranged from 0 to 31
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*
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* @return argument used by handler of passed interrupt number
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*/
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static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
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{
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return intr_handler_get_arg(intr);
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}
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/**
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* @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
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*
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* @param intr interrupt number ranged from 0 to 31
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*/
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static inline void intr_cntrl_ll_edge_int_acknowledge(int intr)
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{
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REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr);
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}
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/**
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* @brief Sets the interrupt level int the interrupt controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param level priority between 1 (lowest) to 7 (highest)
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*/
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static inline void intr_cntrl_ll_set_int_level(int intr, int level)
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{
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esprv_intc_int_set_priority(intr, level);
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}
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/**
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* @brief Set the type of an interrupt in the controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param type interrupt type as edge or level triggered
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*/
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static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
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{
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esprv_intc_int_set_type(BIT(intr), type);
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}
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#ifdef __cplusplus
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}
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#endif
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