kopia lustrzana https://github.com/espressif/esp-idf
257 wiersze
12 KiB
C
257 wiersze
12 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#include "esp_assert.h"
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#endif
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#include "esp_bit_defs.h"
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#include "reg_base.h"
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#define PRO_CPU_NUM (0)
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#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6
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#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1
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#define UART_FIFO_AHB_REG(i) (REG_UART_BASE(i) + 0x0)
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#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
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#define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
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#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
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#define REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000)
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#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE + (i) * 0x1000)
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#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x1000) // TWAI0 and TWAI1
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#ifndef __ASSEMBLER__
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//write value to register
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#define REG_WRITE(_r, _v) do { \
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(*(volatile uint32_t *)(_r)) = (_v); \
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} while(0)
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//read value from register
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#define REG_READ(_r) ({ \
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(*(volatile uint32_t *)(_r)); \
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})
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//get bit or get bits from register
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#define REG_GET_BIT(_r, _b) ({ \
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(*(volatile uint32_t*)(_r) & (_b)); \
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})
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//set bit or set bits to register
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#define REG_SET_BIT(_r, _b) do { \
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*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \
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} while(0)
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//clear bit or clear bits of register
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#define REG_CLR_BIT(_r, _b) do { \
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*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \
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} while(0)
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//set bits of register controlled by mask
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#define REG_SET_BITS(_r, _b, _m) do { \
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*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \
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} while(0)
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//get field from register, uses field _S & _V to determine mask
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#define REG_GET_FIELD(_r, _f) ({ \
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((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
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})
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//set field of a register from variable, uses field _S & _V to determine mask
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#define REG_SET_FIELD(_r, _f, _v) do { \
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REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \
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} while(0)
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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//get field value from a variable, used when _f is left shifted by _f##_S
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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//set field value to a variable, used when _f is not left shifted by _f##_S
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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//set field value to a variable, used when _f is left shifted by _f##_S
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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//generate a value from a field value, used when _f is not left shifted by _f##_S
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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//read value from register
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#define READ_PERI_REG(addr) ({ \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
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})
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//write value to register
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#define WRITE_PERI_REG(addr, val) do { \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
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} while(0)
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//clear bits of register controlled by mask
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#define CLEAR_PERI_REG_MASK(reg, mask) do { \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
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} while(0)
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//set bits of register controlled by mask
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#define SET_PERI_REG_MASK(reg, mask) do { \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
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} while(0)
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//get bits of register controlled by mask
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#define GET_PERI_REG_MASK(reg, mask) ({ \
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(READ_PERI_REG(reg) & (mask)); \
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})
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//get bits of register controlled by highest bit and lowest bit
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#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
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((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
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})
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//set bits of register controlled by mask and shift
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#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \
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WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \
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} while(0)
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//get field of register
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#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
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((READ_PERI_REG(reg)>>(shift))&(mask)); \
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})
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#endif /* !__ASSEMBLER__ */
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//}}
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//Periheral Clock {{
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#define APB_CLK_FREQ_ROM ( 10*1000000 )
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#define CPU_CLK_FREQ_ROM ( 40*1000000 )
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#define CPU_CLK_FREQ_MHZ_BTLD (90) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
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#define APB_CLK_FREQ ( 90*1000000 )
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#define REF_CLK_FREQ ( 1000000 )
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#define XTAL_CLK_FREQ (40*1000000)
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#define GPIO_MATRIX_DELAY_NS 0
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//}}
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/* Overall memory map */
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/* Note: We should not use MACROs similar in cache_memory.h
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* those are defined during run-time. But the MACROs here
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* should be defined statically!
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*/
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#define SOC_IROM_LOW 0x40000000
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#define SOC_IROM_HIGH 0x44000000
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#define SOC_DROM_LOW 0x40000000
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#define SOC_DROM_HIGH 0x44000000
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#define SOC_EXTRAM_LOW 0x48000000
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#define SOC_EXTRAM_HIGH 0x4c000000
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#define SOC_EXTRAM_SIZE (SOC_EXTRAM_HIGH - SOC_EXTRAM_LOW)
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#define SOC_IROM_MASK_LOW 0x4fc00000
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#define SOC_IROM_MASK_HIGH 0x4fc20000
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#define SOC_DROM_MASK_LOW 0x4fc00000
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#define SOC_DROM_MASK_HIGH 0x4fc20000
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#define SOC_TCM_LOW 0x30100000
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#define SOC_TCM_HIGH 0x30102000
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#define SOC_IRAM_LOW 0x4ff00000
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#define SOC_IRAM_HIGH 0x4ffc0000
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#define SOC_DRAM_LOW 0x4ff00000
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#define SOC_DRAM_HIGH 0x4ffc0000
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#define SOC_RTC_IRAM_LOW 0x50108000 // ESP32-P4 only has 32k LP memory
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#define SOC_RTC_IRAM_HIGH 0x50110000
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#define SOC_RTC_DRAM_LOW 0x50108000
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#define SOC_RTC_DRAM_HIGH 0x50110000
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#define SOC_RTC_DATA_LOW 0x50108000
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#define SOC_RTC_DATA_HIGH 0x50110000
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#define SOC_LP_ROM_LOW 0x50100000
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#define SOC_LP_ROM_HIGH 0x50104000
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#define SOC_LP_RAM_LOW 0x50108000
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#define SOC_LP_RAM_HIGH 0x50110000
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//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
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#define SOC_DIRAM_IRAM_LOW 0x4ff00000
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#define SOC_DIRAM_IRAM_HIGH 0x4ffc0000
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#define SOC_DIRAM_DRAM_LOW 0x4ff00000
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#define SOC_DIRAM_DRAM_HIGH 0x4ffc0000
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#define SOC_DIRAM_ROM_RESERVE_HIGH 0x4ff40000
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// Region of memory accessible via DMA. See esp_ptr_dma_capable().
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#define SOC_DMA_LOW 0x4ff00000
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#define SOC_DMA_HIGH 0x4ffc0000
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// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
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#define SOC_BYTE_ACCESSIBLE_LOW 0x4ff00000
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#define SOC_BYTE_ACCESSIBLE_HIGH 0x4ffc0000
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//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
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//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
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#define SOC_MEM_INTERNAL_LOW 0x4ff00000
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#define SOC_MEM_INTERNAL_HIGH 0x4ffc0000
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#define SOC_MEM_INTERNAL_LOW1 0x4ff00000
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#define SOC_MEM_INTERNAL_HIGH1 0x4ffc0000
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#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_HIGH - SOC_EXTRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
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#define CPU_PERIPH_LOW 0x3ff00000
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#define CPU_PERIPH_HIGH 0x3ff20000
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// Region of address space that holds peripherals, HP APB peripherals
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#define SOC_PERIPHERAL_LOW 0x50000000
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#define SOC_PERIPHERAL_HIGH 0x50100000
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#define SOC_LP_PERIPH_LOW 0x50110000
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#define SOC_LP_PERIPH_HIGH 0x50130000
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// CPU sub-system region, contains interrupt config registers
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#define SOC_CPU_SUBSYSTEM_LOW 0x20000000
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#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
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// Start (highest address) of ROM boot stack, only relevant during early boot
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#define SOC_ROM_STACK_START 0x4ff3cfc0
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#define SOC_ROM_STACK_SIZE 0x2000
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//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
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//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
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//CPU0 Interrupt number reserved in riscv/vector_clic.S, do not touch this.
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#define ETS_T1_WDT_INUM 24
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#define ETS_CACHEERR_INUM 25
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#define ETS_MEMPROT_ERR_INUM 26
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#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated
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#define ETS_IPC_ISR_INUM 28
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//CPU0 Max valid interrupt number
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#define ETS_MAX_INUM 31
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//CPU0 Interrupt number used in ROM, should be cancelled in SDK
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#define ETS_SLC_INUM 1
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#define ETS_UART0_INUM 5
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#define ETS_UART1_INUM 5
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#define ETS_SPI2_INUM 1
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//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
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#define ETS_GPIO_INUM 4
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//Other interrupt number should be managed by the user
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//Invalid interrupt for number interrupt matrix
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#define ETS_INVALID_INUM 0
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//Interrupt medium level, used for INT WDT for example
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#define SOC_INTERRUPT_LEVEL_MEDIUM 4
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// Interrupt number for the Interrupt watchdog
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#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)
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