kopia lustrzana https://github.com/espressif/esp-idf
126 wiersze
5.9 KiB
ArmAsm
126 wiersze
5.9 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "soc/soc.h"
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/* If memory protection interrupts are meant to trigger a panic, attach them to panic handler,
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* else, attach them to the interrupt handler. */
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#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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#define MEMPROT_ISR _panic_handler
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#else
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#define MEMPROT_ISR _interrupt_handler
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#endif // CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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#define ASTDBG_ISR _panic_handler
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#else
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#define ASTDBG_ISR _interrupt_handler
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#endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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#if CONFIG_ESP_IPC_ISR_ENABLE
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#define IPC_ISR_HANDLER esp_ipc_isr_handler
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#else
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#define IPC_ISR_HANDLER _interrupt_handler
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#endif // CONFIG_ESP_IPC_ISR_ENABLE
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/* The system interrupts are not used for now, so trigger a panic every time one occurs. */
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#define _system_int_handler _panic_handler
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/* Handlers defined in the `vector.S` file, common to all RISC-V targets */
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.global _interrupt_handler
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.global _panic_handler
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.section .exception_vectors_table.text
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/* Prevent the compiler from generating 2-byte instruction in the vector tables */
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.option push
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.option norvc
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/**
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* Non-hardware vectored interrupt entry. MTVEC CSR points here.
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*
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* On targets that use CLIC as their interrupt controller, when an exception occurs, the CPU
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* jumps to the address stored in MTVEC[31:6] << 6. The CPU will also jump to this location
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* if an interrupt is configured as non-vectored (CLIC_INT_ATTR.shv = 0).
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*
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* Because of the left-shift `<< 6`, this entry must be aligned on 64.
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*/
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.global _vector_table
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.type _vector_table, @function
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.balign 0x40
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_vector_table:
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j _panic_handler
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.size _vector_table, .-_vector_table
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/**
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* Vectored interrupt table. MTVT CSR points here.
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*
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* If an interrupt occurs and is configured as (hardware) vectored, the CPU will jump to
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* MTVT[31:0] + 4 * interrupt_id
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*
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* In the case of the ESP32P4, the interrupt matrix, between the CPU interrupt lines
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* and the peripherals, offers 32 lines. As such, the interrupt_id between 0 and 31.
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*
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* Since the interrupts are initialized as vectored on CPU start, we can manage the special
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* interrupts ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_MEMPROT_ERR_INUM here.
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*/
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.balign 0x40
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.global _mtvt_table
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.type _mtvt_table, @function
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_mtvt_table:
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.word _system_int_handler /* 0: System interrupt number. Exceptions are non-vectored, won't load this. */
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.word _system_int_handler /* 1: System interrupt number */
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.word _system_int_handler /* 2: System interrupt number */
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.word _system_int_handler /* 3: System interrupt number */
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.word _system_int_handler /* 4: System interrupt number */
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.word _system_int_handler /* 5: System interrupt number */
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.word _system_int_handler /* 6: System interrupt number */
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.word _system_int_handler /* 7: System interrupt number */
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.word _system_int_handler /* 8: System interrupt number */
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.word _system_int_handler /* 9: System interrupt number */
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.word _system_int_handler /* 10: System interrupt number */
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.word _system_int_handler /* 11: System interrupt number */
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.word _system_int_handler /* 12: System interrupt number */
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.word _system_int_handler /* 13: System interrupt number */
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.word _system_int_handler /* 14: System interrupt number */
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.word _system_int_handler /* 15: System interrupt number */
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.word _interrupt_handler /* 16: Free interrupt number */
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.word _interrupt_handler /* 17: Free interrupt number */
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.word _interrupt_handler /* 18: Free interrupt number */
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.word _interrupt_handler /* 19: Free interrupt number */
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.word _interrupt_handler /* 20: Free interrupt number */
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.word _interrupt_handler /* 21: Free interrupt number */
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.word _interrupt_handler /* 22: Free interrupt number */
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.word _interrupt_handler /* 23: Free interrupt number */
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.word _interrupt_handler /* 24: Free interrupt number */
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.word _interrupt_handler /* 25: Free interrupt number */
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.word _interrupt_handler /* 26: Free interrupt number */
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.word _interrupt_handler /* 27: Free interrupt number */
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.word _interrupt_handler /* 28: Free interrupt number */
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.word _interrupt_handler /* 29: Free interrupt number */
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.word _interrupt_handler /* 30: Free interrupt number */
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.word _interrupt_handler /* 31: Free interrupt number */
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.word _interrupt_handler /* 32: Free interrupt number */
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.word _interrupt_handler /* 33: Free interrupt number */
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.word _interrupt_handler /* 34: Free interrupt number */
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.word _interrupt_handler /* 35: Free interrupt number */
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.word _interrupt_handler /* 36: Free interrupt number */
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.word _interrupt_handler /* 37: Free interrupt number */
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.word _interrupt_handler /* 38: Free interrupt number */
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.word _interrupt_handler /* 39: Free interrupt number */
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.word _panic_handler /* 40: ETS_INT_WDT_INUM (+16) panic-interrupt (soc-level panic) */
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.word _panic_handler /* 41: ETS_CACHEERR_INUM (+16) panic-interrupt (soc-level panic) */
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.word MEMPROT_ISR /* 42: ETS_MEMPROT_ERR_INUM (+16) handler (soc-level panic) */
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.word ASTDBG_ISR /* 43: ETS_ASSIST_DEBUG_INUM (+16) handler (soc-level panic) */
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.word IPC_ISR_HANDLER /* 44: ETS_IPC_ISR_INUM (+16) handler*/
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.word _interrupt_handler /* 45: Free interrupt number */
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.word _interrupt_handler /* 46: Free interrupt number */
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.word _interrupt_handler /* 47: Free interrupt number */
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.size _mtvt_table, .-_mtvt_table
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.option pop
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