kopia lustrzana https://github.com/espressif/esp-idf
144 wiersze
5.5 KiB
C
144 wiersze
5.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for DEBUG_ASSIST peripheral
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#pragma once
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#include "soc/assist_debug_reg.h"
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#define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
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#ifndef __ASSEMBLER__
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#include <stdbool.h>
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#include <stdint.h>
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#include "esp_attr.h"
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#include "hal/assert.h"
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#include "soc/hp_sys_clkrst_struct.h"
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#include "sdkconfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Most other peripherals have 4 interrupt-related registers: INT_ENA_REG, INT_CLR_REG, INT_RAW_REG, INT_ST_REG, the
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* meaning of which is well-understood.
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*
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* Assist_debug peripheral uses a different structure of interrupt registers:
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* INT_ENA_REG, INT_RLS_REG, INT_CLR_REG, INT_RAW_REG.
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*
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* Their behavior can be explained using the following (verilog-like) pseudo-code:
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* reg sp_spill_max_st
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* assign sp_spill_max = (sp > SP_MAX_REG)
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* assign SP_SPILL_MAX_RAW = sp_spill_max & SPILL_MAX_ENA
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* always (@posedge clk) begin
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* if (reset) then sp_spill_max_st <= 0
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* elif SP_SPILL_MAX_CLR then sp_spill_max_st <= 0
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* else sp_spill_max_st <= SP_SPILL_MAX_RAW & SP_SPILL_MAX_RLS
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* end
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* // ...same for sp_spill_min and other things dsoc/hp_sys_clkrst_struct.hebug_assist can check.
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*
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* // this is the final interrupt line coming out of the peripheral:
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* assign DEBUG_ASSIST_INT = sp_spill_max_st | sp_spill_min_st | ...
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*
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* Basically, there is no "ST" register showing the final (latched) interrupt state, and there is an additional
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* "RLS" register which just like "ENA" can be used to mask the interrupt.
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* Note that writing to CLR clears the (internal) latched interrupt state 'sp_spill_max_st',
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* but doesn't affect the software-readable RAW register.
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*
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* In this code, we use "ENA" to enable monitoring of a particular condition, and "RLS" to enable the interrupt.
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* This allows checking whether the condition (e.g. sp > SP_MAX) has occurred by reading the RAW register, without
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* actually triggering the interrupt. Hence you will see the somewhat counter-intuitive use of "RLS" to enable the
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* interrupt, instead of "ENA".
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*/
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/* These functions are optimized and designed for internal usage.
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* So, the API may differ from general ll layer pattern */
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FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id)
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{
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REG_SET_BIT(core_id ? ASSIST_DEBUG_CORE_1_INTR_ENA_REG : ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
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}
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FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(uint32_t core_id)
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{
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REG_CLR_BIT(core_id ? ASSIST_DEBUG_CORE_1_INTR_ENA_REG : ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS);
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}
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FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(uint32_t core_id)
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{
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REG_SET_BIT(core_id ? ASSIST_DEBUG_CORE_1_INTR_RLS_REG : ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS);
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}
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FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(uint32_t core_id)
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{
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REG_CLR_BIT(core_id ? ASSIST_DEBUG_CORE_1_INTR_RLS_REG : ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS);
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}
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FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(uint32_t core_id)
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{
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return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_INTR_RAW_REG : ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS;
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}
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FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(uint32_t core_id)
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{
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REG_WRITE(core_id ? ASSIST_DEBUG_CORE_1_INTR_CLR_REG : ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS);
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}
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FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(uint32_t core_id, uint32_t min)
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{
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REG_WRITE(core_id ? ASSIST_DEBUG_CORE_1_SP_MIN_REG : ASSIST_DEBUG_CORE_0_SP_MIN_REG, min);
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}
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FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(uint32_t core_id)
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{
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return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_SP_MIN_REG : ASSIST_DEBUG_CORE_0_SP_MIN_REG);
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}
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FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(uint32_t core_id, uint32_t max)
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{
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REG_WRITE(core_id ? ASSIST_DEBUG_CORE_1_SP_MAX_REG : ASSIST_DEBUG_CORE_0_SP_MAX_REG, max);
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}
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FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(uint32_t core_id)
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{
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return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_SP_MAX_REG : ASSIST_DEBUG_CORE_0_SP_MAX_REG);
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}
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FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id)
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{
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return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_SP_PC_REG : ASSIST_DEBUG_CORE_0_SP_PC_REG);
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}
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FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)
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{
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HP_SYS_CLKRST.soc_clk_ctrl0.reg_busmon_cpu_clk_en = enable;
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}
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#define assist_debug_ll_enable_bus_clock(...) \
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(void)__DECLARE_RCC_ATOMIC_ENV; assist_debug_ll_enable_bus_clock(__VA_ARGS__)
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FORCE_INLINE_ATTR void assist_debug_ll_reset_register(void)
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{
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/* esp32p4 has no assist_debug reset register: disable & clear interrupts manually. */
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for (int i = 0; i < CONFIG_SOC_CPU_CORES_NUM; i++) {
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assist_debug_ll_sp_spill_monitor_disable(i);
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assist_debug_ll_sp_spill_interrupt_clear(i);
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assist_debug_ll_sp_spill_set_min(i, 0);
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assist_debug_ll_sp_spill_set_max(i, 0xffffffff);
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/* Enable PC register storing when trigger stack monitor. */
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REG_WRITE(i ? ASSIST_DEBUG_CORE_1_RCD_EN_REG : ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_1_RCD_RECORDEN);
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}
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}
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#define assist_debug_ll_reset_register(...) \
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(void)__DECLARE_RCC_ATOMIC_ENV; assist_debug_ll_reset_register(__VA_ARGS__)
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#ifdef __cplusplus
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}
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#endif
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#endif // __ASSEMBLER__
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