kopia lustrzana https://github.com/espressif/esp-idf
137 wiersze
4.3 KiB
C
137 wiersze
4.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifndef __ASSEMBLER__
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#include "sdkconfig.h"
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#include <stdbool.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ESP_HW_STACK_GUARD_NOT_FIRED UINT32_MAX
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/* The functions below are designed to be used in interrupt/panic handler
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* In case using them in user's code put them into critical section.*/
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void esp_hw_stack_guard_monitor_start(void);
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void esp_hw_stack_guard_monitor_stop(void);
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void esp_hw_stack_guard_set_bounds(uint32_t sp_min, uint32_t sp_max);
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void esp_hw_stack_guard_get_bounds(uint32_t core_id, uint32_t *sp_min, uint32_t *sp_max);
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uint32_t esp_hw_stack_guard_get_fired_cpu(void);
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uint32_t esp_hw_stack_guard_get_pc(uint32_t core_id);
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#ifdef __cplusplus
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};
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#endif
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#else // __ASSEMBLER__
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#include "hal/assist_debug_ll.h"
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#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM (ASSIST_DEBUG_CORE_0_INTR_ENA_REG >> 12)
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#define ASSIST_DEBUG_CORE_0_SP_MIN_OFFSET (ASSIST_DEBUG_CORE_0_SP_MIN_REG - DR_REG_ASSIST_DEBUG_BASE)
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#define ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET (ASSIST_DEBUG_CORE_0_SP_MAX_REG - DR_REG_ASSIST_DEBUG_BASE)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET (ASSIST_DEBUG_CORE_0_INTR_ENA_REG - DR_REG_ASSIST_DEBUG_BASE)
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.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0 reg1
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lui \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
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sw a0, ASSIST_DEBUG_CORE_0_SP_MIN_OFFSET(\reg1)
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sw a1, ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET(\reg1)
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.endm
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.macro ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0 reg1 reg2
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lui \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
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lw \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
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andi \reg2, \reg2, ~ASSIST_DEBUG_SP_SPILL_BITS
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sw \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
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.endm
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.macro ESP_HW_STACK_GUARD_MONITOR_START_CPU0 reg1 reg2
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lui \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
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lw \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
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ori \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
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sw \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
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.endm
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#if SOC_CPU_CORES_NUM > 1
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#define ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM (ASSIST_DEBUG_CORE_1_INTR_ENA_REG >> 12)
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#define ASSIST_DEBUG_CORE_1_SP_MIN_OFFSET (ASSIST_DEBUG_CORE_1_SP_MIN_REG - DR_REG_ASSIST_DEBUG_BASE)
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#define ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET (ASSIST_DEBUG_CORE_1_SP_MAX_REG - DR_REG_ASSIST_DEBUG_BASE)
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#define ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET (ASSIST_DEBUG_CORE_1_INTR_ENA_REG - DR_REG_ASSIST_DEBUG_BASE)
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.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CPU1 reg1
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lui \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
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sw a0, ASSIST_DEBUG_CORE_1_SP_MIN_OFFSET(\reg1)
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sw a1, ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET(\reg1)
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.endm
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.macro ESP_HW_STACK_GUARD_MONITOR_STOP_CPU1 reg1 reg2
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lui \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
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lw \reg2, ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET(\reg1)
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andi \reg2, \reg2, ~ASSIST_DEBUG_SP_SPILL_BITS
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sw \reg2, ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET(\reg1)
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.endm
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.macro ESP_HW_STACK_GUARD_MONITOR_START_CPU1 reg1 reg2
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lui \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
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lw \reg2, ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET(\reg1)
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ori \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
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sw \reg2, ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET(\reg1)
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.endm
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.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE reg1
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/* Check the current core ID */
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csrr \reg1, mhartid
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beqz \reg1, 1f
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/* Core 1 */
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ESP_HW_STACK_GUARD_SET_BOUNDS_CPU1 \reg1
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j 2f
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1:
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/* Core 0 */
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ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0 \reg1
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2:
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.endm
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.macro ESP_HW_STACK_GUARD_MONITOR_START_CUR_CORE reg1 reg2
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/* Check the current core ID */
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csrr \reg1, mhartid
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beqz \reg1, 1f
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/* Core 1 */
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ESP_HW_STACK_GUARD_MONITOR_START_CPU1 \reg1 \reg2
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j 2f
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1:
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/* Core 0 */
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ESP_HW_STACK_GUARD_MONITOR_START_CPU0 \reg1 \reg2
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2:
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.endm
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.macro ESP_HW_STACK_GUARD_MONITOR_STOP_CUR_CORE reg1 reg2
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/* Check the current core ID */
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csrr \reg1, mhartid
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beqz \reg1, 1f
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/* Core 1 */
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ESP_HW_STACK_GUARD_MONITOR_STOP_CPU1 \reg1 \reg2
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j 2f
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1:
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/* Core 0 */
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ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0 \reg1 \reg2
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2:
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.endm
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#else // SOC_CPU_CORES_NUM <= 1
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#define ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0
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#define ESP_HW_STACK_GUARD_MONITOR_START_CUR_CORE ESP_HW_STACK_GUARD_MONITOR_START_CPU0
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#define ESP_HW_STACK_GUARD_MONITOR_STOP_CUR_CORE ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0
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#endif // SOC_CPU_CORES_NUM > 1
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#endif // __ASSEMBLER__
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