kopia lustrzana https://github.com/espressif/esp-idf
69 wiersze
1.6 KiB
C
69 wiersze
1.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp_attr.h"
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#include "soc/hp_system_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Clear the crosscore interrupt that just occurred on the current core
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
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{
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if (core_id == 0) {
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WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG, 0);
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} else {
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WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_1_REG, 0);
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}
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}
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/**
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* @brief Trigger a crosscore interrupt on the given core
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*
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* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
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{
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if (core_id == 0) {
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WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG, HP_SYSTEM_CPU_INT_FROM_CPU_0);
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} else {
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WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_1_REG, HP_SYSTEM_CPU_INT_FROM_CPU_1);
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}
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}
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/**
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* @brief Get the state of the crosscore interrupt register for the given core
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*
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* @param core_id Core to get the crosscore interrupt state of. Ignored on single core targets.
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*
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* @return Non zero value if a software interrupt is pending on the given core,
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* 0 if no software interrupt is pending.
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*/
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FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
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{
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uint32_t reg = 0;
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if (core_id == 0) {
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reg = REG_READ(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG);
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} else {
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reg = REG_READ(HP_SYSTEM_CPU_INT_FROM_CPU_1_REG);
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}
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return reg;
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}
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#ifdef __cplusplus
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}
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#endif
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