kopia lustrzana https://github.com/espressif/esp-idf
586 wiersze
18 KiB
C
586 wiersze
18 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include <assert.h>
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#include "soc/soc_caps.h"
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#ifdef __XTENSA__
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#include "xtensa_api.h"
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#include "xt_utils.h"
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#elif __riscv
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#include "riscv/rv_utils.h"
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#endif
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#include "esp_intr_alloc.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief CPU cycle count type
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*
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* This data type represents the CPU's clock cycle count
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*/
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typedef uint32_t esp_cpu_cycle_count_t;
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/**
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* @brief CPU interrupt type
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*/
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typedef enum {
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ESP_CPU_INTR_TYPE_LEVEL = 0,
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ESP_CPU_INTR_TYPE_EDGE,
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ESP_CPU_INTR_TYPE_NA,
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} esp_cpu_intr_type_t;
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/**
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* @brief CPU interrupt descriptor
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*
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* Each particular CPU interrupt has an associated descriptor describing that
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* particular interrupt's characteristics. Call esp_cpu_intr_get_desc() to get
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* the descriptors of a particular interrupt.
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*/
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typedef struct {
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int priority; /**< Priority of the interrupt if it has a fixed priority, (-1) if the priority is configurable. */
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esp_cpu_intr_type_t type; /**< Whether the interrupt is an edge or level type interrupt, ESP_CPU_INTR_TYPE_NA if the type is configurable. */
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uint32_t flags; /**< Flags indicating extra details. */
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} esp_cpu_intr_desc_t;
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/**
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* @brief Interrupt descriptor flags of esp_cpu_intr_desc_t
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*/
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#define ESP_CPU_INTR_DESC_FLAG_SPECIAL 0x01 /**< The interrupt is a special interrupt (e.g., a CPU timer interrupt) */
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#define ESP_CPU_INTR_DESC_FLAG_RESVD 0x02 /**< The interrupt is reserved for internal use */
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/**
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* @brief CPU interrupt handler type
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*/
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typedef void (*esp_cpu_intr_handler_t)(void *arg);
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/**
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* @brief CPU watchpoint trigger type
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*/
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typedef enum {
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ESP_CPU_WATCHPOINT_LOAD,
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ESP_CPU_WATCHPOINT_STORE,
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ESP_CPU_WATCHPOINT_ACCESS,
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} esp_cpu_watchpoint_trigger_t;
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/* --------------------------------------------------- CPU Control -----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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/**
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* @brief Stall a CPU core
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*
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* @param core_id The core's ID
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*/
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void esp_cpu_stall(int core_id);
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/**
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* @brief Resume a previously stalled CPU core
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*
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* @param core_id The core's ID
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*/
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void esp_cpu_unstall(int core_id);
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/**
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* @brief Reset a CPU core
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*
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* @param core_id The core's ID
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*/
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void esp_cpu_reset(int core_id);
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/**
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* @brief Wait for Interrupt
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*
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* This function causes the current CPU core to execute its Wait For Interrupt
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* (WFI or equivalent) instruction. After executing this function, the CPU core
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* will stop execution until an interrupt occurs.
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*/
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void esp_cpu_wait_for_intr(void);
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/* -------------------------------------------------- CPU Registers ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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/**
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* @brief Get the current core's ID
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*
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* This function will return the ID of the current CPU (i.e., the CPU that calls
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* this function).
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*
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* @return The current core's ID [0..SOC_CPU_CORES_NUM - 1]
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*/
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FORCE_INLINE_ATTR __attribute__((pure)) int esp_cpu_get_core_id(void)
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{
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//Note: Made "pure" to optimize for single core target
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#ifdef __XTENSA__
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return (int)xt_utils_get_core_id();
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#else
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return (int)rv_utils_get_core_id();
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#endif
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}
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/**
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* @brief Read the current stack pointer address
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*
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* @return Stack pointer address
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*/
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FORCE_INLINE_ATTR void *esp_cpu_get_sp(void)
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{
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#ifdef __XTENSA__
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return xt_utils_get_sp();
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#else
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return rv_utils_get_sp();
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#endif
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}
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/**
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* @brief Get the current CPU core's cycle count
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*
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* Each CPU core maintains an internal counter (i.e., cycle count) that increments
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* every CPU clock cycle.
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*
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* @return Current CPU's cycle count, 0 if not supported.
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*/
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FORCE_INLINE_ATTR esp_cpu_cycle_count_t esp_cpu_get_cycle_count(void)
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{
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#ifdef __XTENSA__
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return (esp_cpu_cycle_count_t)xt_utils_get_cycle_count();
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#else
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return (esp_cpu_cycle_count_t)rv_utils_get_cycle_count();
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#endif
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}
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/**
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* @brief Set the current CPU core's cycle count
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*
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* Set the given value into the internal counter that increments every
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* CPU clock cycle.
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*
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* @param cycle_count CPU cycle count
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*/
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FORCE_INLINE_ATTR void esp_cpu_set_cycle_count(esp_cpu_cycle_count_t cycle_count)
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{
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#ifdef __XTENSA__
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xt_utils_set_cycle_count((uint32_t)cycle_count);
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#else
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rv_utils_set_cycle_count((uint32_t)cycle_count);
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#endif
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}
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/**
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* @brief Convert a program counter (PC) value to address
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*
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* If the architecture does not store the true virtual address in the CPU's PC
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* or return addresses, this function will convert the PC value to a virtual
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* address. Otherwise, the PC is just returned
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*
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* @param pc PC value
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* @return Virtual address
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*/
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FORCE_INLINE_ATTR __attribute__((pure)) void *esp_cpu_pc_to_addr(uint32_t pc)
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{
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#ifdef __XTENSA__
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// Xtensa stores window rotation in PC[31:30]
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return (void *)((pc & 0x3fffffffU) | 0x40000000U);
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#else
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return (void *)pc;
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#endif
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}
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/* ------------------------------------------------- CPU Interrupts ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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// ---------------- Interrupt Descriptors ------------------
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/**
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* @brief Get a CPU interrupt's descriptor
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*
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* Each CPU interrupt has a descriptor describing the interrupt's capabilities
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* and restrictions. This function gets the descriptor of a particular interrupt
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* on a particular CPU.
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*
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* @param[in] core_id The core's ID
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* @param[in] intr_num Interrupt number
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* @param[out] intr_desc_ret The interrupt's descriptor
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*/
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void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret);
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// --------------- Interrupt Configuration -----------------
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/**
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* @brief Set the base address of the current CPU's Interrupt Vector Table (IVT)
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*
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* @param ivt_addr Interrupt Vector Table's base address
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*/
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FORCE_INLINE_ATTR void esp_cpu_intr_set_ivt_addr(const void *ivt_addr)
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{
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#ifdef __XTENSA__
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xt_utils_set_vecbase((uint32_t)ivt_addr);
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#else
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rv_utils_set_mtvec((uint32_t)ivt_addr);
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#endif
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}
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#if SOC_INT_CLIC_SUPPORTED
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/**
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* @brief Set the base address of the current CPU's Interrupt Vector Table (MTVT)
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*
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* @param mtvt_addr Interrupt Vector Table's base address
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*
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* @note The MTVT table is only applicable when CLIC is supported
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*/
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FORCE_INLINE_ATTR void esp_cpu_intr_set_mtvt_addr(const void *mtvt_addr)
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{
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rv_utils_set_mtvt((uint32_t)mtvt_addr);
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}
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#endif //#if SOC_INT_CLIC_SUPPORTED
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#if SOC_CPU_HAS_FLEXIBLE_INTC
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/**
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* @brief Set the interrupt type of a particular interrupt
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*
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* Set the interrupt type (Level or Edge) of a particular interrupt on the
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* current CPU.
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*
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* @param intr_num Interrupt number (from 0 to 31)
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* @param intr_type The interrupt's type
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*/
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FORCE_INLINE_ATTR void esp_cpu_intr_set_type(int intr_num, esp_cpu_intr_type_t intr_type)
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{
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assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
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enum intr_type type = (intr_type == ESP_CPU_INTR_TYPE_LEVEL) ? INTR_TYPE_LEVEL : INTR_TYPE_EDGE;
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esprv_int_set_type(intr_num, type);
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}
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/**
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* @brief Get the current configured type of a particular interrupt
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*
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* Get the currently configured type (i.e., level or edge) of a particular
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* interrupt on the current CPU.
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*
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* @param intr_num Interrupt number (from 0 to 31)
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* @return Interrupt type
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*/
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FORCE_INLINE_ATTR esp_cpu_intr_type_t esp_cpu_intr_get_type(int intr_num)
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{
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assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
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enum intr_type type = esprv_int_get_type(intr_num);
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return (type == INTR_TYPE_LEVEL) ? ESP_CPU_INTR_TYPE_LEVEL : ESP_CPU_INTR_TYPE_EDGE;
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}
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/**
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* @brief Set the priority of a particular interrupt
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*
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* Set the priority of a particular interrupt on the current CPU.
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*
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* @param intr_num Interrupt number (from 0 to 31)
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* @param intr_priority The interrupt's priority
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*/
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FORCE_INLINE_ATTR void esp_cpu_intr_set_priority(int intr_num, int intr_priority)
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{
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assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
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esprv_int_set_priority(intr_num, intr_priority);
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}
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/**
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* @brief Get the current configured priority of a particular interrupt
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*
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* Get the currently configured priority of a particular interrupt on the
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* current CPU.
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*
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* @param intr_num Interrupt number (from 0 to 31)
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* @return Interrupt's priority
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*/
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FORCE_INLINE_ATTR int esp_cpu_intr_get_priority(int intr_num)
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{
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assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
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return esprv_int_get_priority(intr_num);
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}
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#endif // SOC_CPU_HAS_FLEXIBLE_INTC
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/**
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* @brief Check if a particular interrupt already has a handler function
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*
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* Check if a particular interrupt on the current CPU already has a handler
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* function assigned.
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*
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* @note This function simply checks if the IVT of the current CPU already has
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* a handler assigned.
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* @param intr_num Interrupt number (from 0 to 31)
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* @return True if the interrupt has a handler function, false otherwise.
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*/
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FORCE_INLINE_ATTR bool esp_cpu_intr_has_handler(int intr_num)
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{
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assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
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bool has_handler;
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#ifdef __XTENSA__
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has_handler = xt_int_has_handler(intr_num, esp_cpu_get_core_id());
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#else
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has_handler = intr_handler_get(intr_num);
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#endif
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return has_handler;
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}
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/**
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* @brief Set the handler function of a particular interrupt
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*
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* Assign a handler function (i.e., ISR) to a particular interrupt on the
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* current CPU.
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*
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* @note This function simply sets the handler function (in the IVT) and does
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* not actually enable the interrupt.
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* @param intr_num Interrupt number (from 0 to 31)
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* @param handler Handler function
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* @param handler_arg Argument passed to the handler function
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*/
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FORCE_INLINE_ATTR void esp_cpu_intr_set_handler(int intr_num, esp_cpu_intr_handler_t handler, void *handler_arg)
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{
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assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
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#ifdef __XTENSA__
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xt_set_interrupt_handler(intr_num, (xt_handler)handler, handler_arg);
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#else
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intr_handler_set(intr_num, (intr_handler_t)handler, handler_arg);
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#endif
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}
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/**
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* @brief Get a handler function's argument of
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*
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* Get the argument of a previously assigned handler function on the current CPU.
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*
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* @param intr_num Interrupt number (from 0 to 31)
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* @return The the argument passed to the handler function
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*/
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FORCE_INLINE_ATTR void *esp_cpu_intr_get_handler_arg(int intr_num)
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{
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assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
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void *handler_arg;
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#ifdef __XTENSA__
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handler_arg = xt_get_interrupt_handler_arg(intr_num);
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#else
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handler_arg = intr_handler_get_arg(intr_num);
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#endif
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return handler_arg;
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}
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// ------------------ Interrupt Control --------------------
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/**
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* @brief Enable particular interrupts on the current CPU
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*
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* @param intr_mask Bit mask of the interrupts to enable
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*/
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FORCE_INLINE_ATTR void esp_cpu_intr_enable(uint32_t intr_mask)
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{
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#ifdef __XTENSA__
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xt_ints_on(intr_mask);
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#else
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rv_utils_intr_enable(intr_mask);
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#endif
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}
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/**
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* @brief Disable particular interrupts on the current CPU
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*
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* @param intr_mask Bit mask of the interrupts to disable
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*/
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FORCE_INLINE_ATTR void esp_cpu_intr_disable(uint32_t intr_mask)
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{
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#ifdef __XTENSA__
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xt_ints_off(intr_mask);
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#else
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rv_utils_intr_disable(intr_mask);
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#endif
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}
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/**
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* @brief Get the enabled interrupts on the current CPU
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*
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* @return Bit mask of the enabled interrupts
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*/
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FORCE_INLINE_ATTR uint32_t esp_cpu_intr_get_enabled_mask(void)
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{
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#ifdef __XTENSA__
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return xt_utils_intr_get_enabled_mask();
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#else
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return rv_utils_intr_get_enabled_mask();
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#endif
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}
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/**
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* @brief Acknowledge an edge interrupt
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*
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* @param intr_num Interrupt number (from 0 to 31)
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*/
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FORCE_INLINE_ATTR void esp_cpu_intr_edge_ack(int intr_num)
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{
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assert(intr_num >= 0 && intr_num < SOC_CPU_INTR_NUM);
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#ifdef __XTENSA__
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xthal_set_intclear((unsigned) (1 << intr_num));
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#else
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rv_utils_intr_edge_ack((unsigned) intr_num);
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#endif
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}
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/* -------------------------------------------------- Memory Ports -----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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/**
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* @brief Configure the CPU to disable access to invalid memory regions
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*/
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void esp_cpu_configure_region_protection(void);
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/* ---------------------------------------------------- Debugging ------------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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// --------------- Breakpoints/Watchpoints -----------------
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#if SOC_CPU_BREAKPOINTS_NUM > 0
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/**
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* @brief Set and enable a hardware breakpoint on the current CPU
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*
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* @note This function is meant to be called by the panic handler to set a
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* breakpoint for an attached debugger during a panic.
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* @note Overwrites previously set breakpoint with same breakpoint number.
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* @param bp_num Hardware breakpoint number [0..SOC_CPU_BREAKPOINTS_NUM - 1]
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* @param bp_addr Address to set a breakpoint on
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* @return ESP_OK if breakpoint is set. Failure otherwise
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*/
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esp_err_t esp_cpu_set_breakpoint(int bp_num, const void *bp_addr);
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/**
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* @brief Clear a hardware breakpoint on the current CPU
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*
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* @note Clears a breakpoint regardless of whether it was previously set
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* @param bp_num Hardware breakpoint number [0..SOC_CPU_BREAKPOINTS_NUM - 1]
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* @return ESP_OK if breakpoint is cleared. Failure otherwise
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*/
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esp_err_t esp_cpu_clear_breakpoint(int bp_num);
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#endif // SOC_CPU_BREAKPOINTS_NUM > 0
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/**
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* @brief Set and enable a hardware watchpoint on the current CPU
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*
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* Set and enable a hardware watchpoint on the current CPU, specifying the
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* memory range and trigger operation. Watchpoints will break/panic the CPU when
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* the CPU accesses (according to the trigger type) on a certain memory range.
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*
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* @note Overwrites previously set watchpoint with same watchpoint number.
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* On RISC-V chips, this API uses method0(Exact matching) and method1(NAPOT matching) according to the
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* riscv-debug-spec-0.13 specification for address matching.
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* If the watch region size is 1byte, it uses exact matching (method 0).
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* If the watch region size is larger than 1byte, it uses NAPOT matching (method 1). This mode requires
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* the watching region start address to be aligned to the watching region size.
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*
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* @param wp_num Hardware watchpoint number [0..SOC_CPU_WATCHPOINTS_NUM - 1]
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* @param wp_addr Watchpoint's base address, must be naturally aligned to the size of the region
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* @param size Size of the region to watch. Must be one of 2^n and in the range of [1 ... SOC_CPU_WATCHPOINT_MAX_REGION_SIZE]
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* @param trigger Trigger type
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* @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
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*/
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esp_err_t esp_cpu_set_watchpoint(int wp_num, const void *wp_addr, size_t size, esp_cpu_watchpoint_trigger_t trigger);
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/**
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* @brief Clear a hardware watchpoint on the current CPU
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*
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* @note Clears a watchpoint regardless of whether it was previously set
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* @param wp_num Hardware watchpoint number [0..SOC_CPU_WATCHPOINTS_NUM - 1]
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* @return ESP_OK if watchpoint was cleared. Failure otherwise.
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*/
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esp_err_t esp_cpu_clear_watchpoint(int wp_num);
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// ---------------------- Debugger -------------------------
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/**
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* @brief Check if the current CPU has a debugger attached
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*
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* @return True if debugger is attached, false otherwise
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*/
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FORCE_INLINE_ATTR bool esp_cpu_dbgr_is_attached(void)
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{
|
|
#ifdef __XTENSA__
|
|
return xt_utils_dbgr_is_attached();
|
|
#else
|
|
return rv_utils_dbgr_is_attached();
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* @brief Trigger a call to the current CPU's attached debugger
|
|
*/
|
|
FORCE_INLINE_ATTR void esp_cpu_dbgr_break(void)
|
|
{
|
|
#ifdef __XTENSA__
|
|
xt_utils_dbgr_break();
|
|
#else
|
|
rv_utils_dbgr_break();
|
|
#endif
|
|
}
|
|
|
|
// ---------------------- Instructions -------------------------
|
|
|
|
/**
|
|
* @brief Given the return address, calculate the address of the preceding call instruction
|
|
* This is typically used to answer the question "where was the function called from?"
|
|
* @param return_address The value of the return address register.
|
|
* Typically set to the value of __builtin_return_address(0).
|
|
* @return Address of the call instruction preceding the return address.
|
|
*/
|
|
FORCE_INLINE_ATTR intptr_t esp_cpu_get_call_addr(intptr_t return_address)
|
|
{
|
|
/* Both Xtensa and RISC-V have 2-byte instructions, so to get this right we
|
|
* should decode the preceding instruction as if it is 2-byte, check if it is a call,
|
|
* else treat it as 3 or 4 byte one. However for the cases where this function is
|
|
* used, being off by one instruction is usually okay, so this is kept simple for now.
|
|
*/
|
|
#ifdef __XTENSA__
|
|
return return_address - 3;
|
|
#else
|
|
return return_address - 4;
|
|
#endif
|
|
}
|
|
|
|
/* ------------------------------------------------------ Misc ---------------------------------------------------------
|
|
*
|
|
* ------------------------------------------------------------------------------------------------------------------ */
|
|
|
|
/**
|
|
* @brief Atomic compare-and-set operation
|
|
*
|
|
* @param addr Address of atomic variable
|
|
* @param compare_value Value to compare the atomic variable to
|
|
* @param new_value New value to set the atomic variable to
|
|
* @return Whether the atomic variable was set or not
|
|
*/
|
|
bool esp_cpu_compare_and_set(volatile uint32_t *addr, uint32_t compare_value, uint32_t new_value);
|
|
|
|
#if SOC_BRANCH_PREDICTOR_SUPPORTED
|
|
/**
|
|
* @brief Enable branch prediction
|
|
*/
|
|
FORCE_INLINE_ATTR void esp_cpu_branch_prediction_enable(void)
|
|
{
|
|
rv_utils_en_branch_predictor();
|
|
}
|
|
#endif //#if SOC_BRANCH_PREDICTOR_SUPPORTED
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|