kopia lustrzana https://github.com/espressif/esp-idf
74 wiersze
2.9 KiB
C
74 wiersze
2.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/* SPI commands (actual on-wire commands not SPI controller bitmasks)
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Suitable for use with spi_flash_hal_common_command static function.
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*/
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#define CMD_RDID 0x9F
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#define CMD_RDUID 0x4B /* Read the flash unique ID*/
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#define CMD_WRSR 0x01
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#define SR_WIP (1<<0) /* Status register write-in-progress bit */
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#define SR_WREN (1<<1) /* Status register write enable bit */
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#define CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
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#define CMD_WREN 0x06
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#define CMD_WRDI 0x04
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#define CMD_RDSR 0x05
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#define CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
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#define CMD_RDSCUR 0x2B /* MXIC-specific, read security register */
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#define CMD_8READ 0xEC /* MXIC-specific, 8 I/O read */
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#define CMD_8DTRD 0xEE /* MXIC-specific, 8 I/O DTR read */
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#define CMD_RDFR 0x48 /* ISSI-specific, read function register */
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#define CMD_FASTRD_QIO 0xEB
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#define CMD_FASTRD_QIO_4B 0xEC
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#define CMD_FASTRD_QUAD 0x6B
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#define CMD_FASTRD_QUAD_4B 0x6C
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#define CMD_FASTRD_DIO 0xBB
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#define CMD_FASTRD_DIO_4B 0xBC
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#define CMD_FASTRD_DUAL 0x3B
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#define CMD_FASTRD_DUAL_4B 0x3C
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#define CMD_FASTRD 0x0B
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#define CMD_FASTRD_4B 0x0C
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#define CMD_READ 0x03 /* Speed limited */
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#define CMD_READ_4B 0x13 /* Speed limited */
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#define CMD_CHIP_ERASE 0xC7
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#define CMD_SECTOR_ERASE 0x20
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#define CMD_SECTOR_ERASE_4B 0x21
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#define CMD_LARGE_BLOCK_ERASE 0xD8 /* 64KB block erase command */
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#define CMD_LARGE_BLOCK_ERASE_4B 0xDC /* 64KB block erase command */
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#define CMD_PROGRAM_PAGE 0x02
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#define CMD_PROGRAM_PAGE_4B 0x12
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#define CMD_SUSPEND 0x75
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#define CMD_RESUME 0x7A
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#define CMD_HPMEN 0xA3 /* Enable High Performance mode on flash */
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#define CMD_WRAP 0x77
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#define CMD_BURST_RD 0xC0 /* wrap(0x77) and burst read are functionally same. But commands and formats is different */
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#define CMD_RST_EN 0x66
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#define CMD_RST_DEV 0x99
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#define SPI_FLASH_DIO_ADDR_BITLEN 24
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#define SPI_FLASH_DIO_DUMMY_BITLEN 4
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#define SPI_FLASH_QIO_ADDR_BITLEN 24
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#define SPI_FLASH_QIO_DUMMY_BITLEN 6
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#define SPI_FLASH_QOUT_ADDR_BITLEN 24
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#define SPI_FLASH_QOUT_DUMMY_BITLEN 8
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#define SPI_FLASH_DOUT_ADDR_BITLEN 24
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#define SPI_FLASH_DOUT_DUMMY_BITLEN 8
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#define SPI_FLASH_FASTRD_ADDR_BITLEN 24
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#define SPI_FLASH_FASTRD_DUMMY_BITLEN 8
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#define SPI_FLASH_SLOWRD_ADDR_BITLEN 24
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#define SPI_FLASH_SLOWRD_DUMMY_BITLEN 0
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#define SPI_FLASH_OPISTR_ADDR_BITLEN 32
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#define SPI_FLASH_OPISTR_DUMMY_BITLEN 20
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#define SPI_FLASH_OPIDTR_ADDR_BITLEN 32
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#define SPI_FLASH_OPIDTR_DUMMY_BITLEN 40
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#define SPI_FLASH_QIO_HPM_DUMMY_BITLEN 10
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#define SPI_FLASH_DIO_HPM_DUMMY_BITLEN 8
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